Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	166836732	5704916	0	0
clk_enables_rd_A	166836732	47833	0	0
clk_hints_rd_A	166836732	43268	0	0
extclk_ctrl_rd_A	166836732	53959	0	0
extclk_ctrl_regwen_rd_A	166836732	41326	0	0
jitter_enable_rd_A	166836732	58210	0	0
jitter_regwen_rd_A	166836732	46273	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166836732	5704916	0	0
T2	504330	247952	0	0
T3	45663	0	0	0
T10	445868	219328	0	0
T11	0	95597	0	0
T19	87723	0	0	0
T20	2015	0	0	0
T22	0	179064	0	0
T31	1335	0	0	0
T34	1158	0	0	0
T35	1765	0	0	0
T61	1969	0	0	0
T62	0	79715	0	0
T63	0	43484	0	0
T64	0	73149	0	0
T65	0	72161	0	0
T66	0	59556	0	0
T67	0	81473	0	0
T68	1818	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166836732	47833	0	0
T1	119645	20	0	0
T2	504330	0	0	0
T3	45663	0	0	0
T4	7654	0	0	0
T5	208844	0	0	0
T6	2364	0	0	0
T17	1343	0	0	0
T18	1672	0	0	0
T19	87723	0	0	0
T20	2015	0	0	0
T21	0	11	0	0
T44	0	1	0	0
T63	0	888	0	0
T64	0	1504	0	0
T67	0	1894	0	0
T133	0	4	0	0
T134	0	7	0	0
T135	0	1348	0	0
T136	0	3846	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166836732	43268	0	0
T1	119645	4	0	0
T2	504330	0	0	0
T3	45663	0	0	0
T4	7654	0	0	0
T5	208844	0	0	0
T6	2364	0	0	0
T13	0	6	0	0
T17	1343	0	0	0
T18	1672	0	0	0
T19	87723	0	0	0
T20	2015	0	0	0
T21	0	12	0	0
T63	0	834	0	0
T64	0	1306	0	0
T67	0	1641	0	0
T133	0	1	0	0
T134	0	5	0	0
T137	0	1	0	0
T138	0	1	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166836732	53959	0	0
T1	119645	82	0	0
T2	504330	0	0	0
T3	45663	0	0	0
T4	7654	0	0	0
T5	208844	0	0	0
T6	2364	0	0	0
T13	0	63	0	0
T17	1343	0	0	0
T18	1672	0	0	0
T19	87723	0	0	0
T20	2015	0	0	0
T21	0	98	0	0
T34	0	7	0	0
T61	0	8	0	0
T106	0	18	0	0
T139	0	5	0	0
T140	0	67	0	0
T141	0	22	0	0
T142	0	24	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166836732	41326	0	0
T63	0	791	0	0
T64	0	1310	0	0
T67	0	1657	0	0
T84	2008	0	0	0
T93	18140	16	0	0
T94	50316	0	0	0
T95	0	25	0	0
T105	66066	0	0	0
T135	0	1201	0	0
T136	0	3530	0	0
T143	0	12	0	0
T144	0	40	0	0
T145	0	2366	0	0
T146	1213	0	0	0
T147	1801	0	0	0
T148	1609	0	0	0
T149	1479	0	0	0
T150	1200	0	0	0
T151	1501	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166836732	58210	0	0
T1	119645	335	0	0
T2	504330	0	0	0
T3	45663	0	0	0
T4	7654	0	0	0
T5	208844	0	0	0
T6	2364	0	0	0
T13	0	61	0	0
T17	1343	0	0	0
T18	1672	0	0	0
T19	87723	0	0	0
T20	2015	0	0	0
T21	0	450	0	0
T63	0	986	0	0
T64	0	1981	0	0
T67	0	2100	0	0
T109	0	62	0	0
T137	0	61	0	0
T138	0	72	0	0
T152	0	39	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166836732	46273	0	0
T29	0	2119	0	0
T63	202145	904	0	0
T64	226215	1388	0	0
T67	0	1623	0	0
T113	8778	0	0	0
T135	0	1399	0	0
T136	0	3948	0	0
T145	0	2737	0	0
T153	0	3668	0	0
T154	0	3292	0	0
T155	0	1991	0	0
T156	33407	0	0	0
T157	1567	0	0	0
T158	742	0	0	0
T159	1611	0	0	0
T160	28724	0	0	0
T161	1137	0	0	0
T162	60818	0	0	0