Unified Coverage Report :: Module :: clkmgr_div_sva_if

Module : clkmgr_div_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_div2_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_div4_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Module : clkmgr_div_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T17
1	0	Covered	T1,T2,T35
1	1	Covered	T1,T2,T20

---

Assert Coverage for Module : clkmgr_div_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	473979991	4704	0	0
g_div2.Div2Whole_A	473979991	5500	0	0
g_div4.Div4Stepped_A	237252836	4602	0	0
g_div4.Div4Whole_A	237252836	5255	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473979991	4704	0	0
T1	105479	12	0	0
T2	157923	96	0	0
T3	182653	0	0	0
T4	14698	0	0	0
T5	157007	0	0	0
T6	11350	0	0	0
T10	0	77	0	0
T17	2746	0	0	0
T18	7299	0	0	0
T19	76466	0	0	0
T20	4029	1	0	0
T34	0	3	0	0
T35	0	15	0	0
T61	0	5	0	0
T68	0	9	0	0
T77	0	3	0	0
T78	0	10	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473979991	5500	0	0
T1	105479	14	0	0
T2	157923	112	0	0
T3	182653	0	0	0
T4	14698	0	0	0
T5	157007	0	0	0
T6	11350	0	0	0
T10	0	98	0	0
T17	2746	0	0	0
T18	7299	0	0	0
T19	76466	0	0	0
T20	4029	1	0	0
T34	0	3	0	0
T35	0	15	0	0
T61	0	5	0	0
T68	0	11	0	0
T77	0	3	0	0
T78	0	10	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237252836	4602	0	0
T1	527319	12	0	0
T2	789853	95	0	0
T3	91260	0	0	0
T4	3469	0	0	0
T5	78436	0	0	0
T6	5609	0	0	0
T10	0	68	0	0
T17	1340	0	0	0
T18	3582	0	0	0
T19	38180	0	0	0
T20	1991	1	0	0
T34	0	3	0	0
T35	0	15	0	0
T61	0	5	0	0
T68	0	9	0	0
T77	0	2	0	0
T78	0	9	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237252836	5255	0	0
T1	527319	12	0	0
T2	789853	111	0	0
T3	91260	0	0	0
T4	3469	0	0	0
T5	78436	0	0	0
T6	5609	0	0	0
T10	0	77	0	0
T17	1340	0	0	0
T18	3582	0	0	0
T19	38180	0	0	0
T20	1991	1	0	0
T34	0	3	0	0
T35	0	15	0	0
T61	0	5	0	0
T68	0	11	0	0
T77	0	3	0	0
T78	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T17
1	0	Covered	T1,T2,T35
1	1	Covered	T1,T2,T20

---

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	473979991	4704	0	0
g_div2.Div2Whole_A	473979991	5500	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473979991	4704	0	0
T1	105479	12	0	0
T2	157923	96	0	0
T3	182653	0	0	0
T4	14698	0	0	0
T5	157007	0	0	0
T6	11350	0	0	0
T10	0	77	0	0
T17	2746	0	0	0
T18	7299	0	0	0
T19	76466	0	0	0
T20	4029	1	0	0
T34	0	3	0	0
T35	0	15	0	0
T61	0	5	0	0
T68	0	9	0	0
T77	0	3	0	0
T78	0	10	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473979991	5500	0	0
T1	105479	14	0	0
T2	157923	112	0	0
T3	182653	0	0	0
T4	14698	0	0	0
T5	157007	0	0	0
T6	11350	0	0	0
T10	0	98	0	0
T17	2746	0	0	0
T18	7299	0	0	0
T19	76466	0	0	0
T20	4029	1	0	0
T34	0	3	0	0
T35	0	15	0	0
T61	0	5	0	0
T68	0	11	0	0
T77	0	3	0	0
T78	0	10	0	0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T17
1	0	Covered	T1,T2,T35
1	1	Covered	T1,T2,T20

---

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div4.Div4Stepped_A	237252836	4602	0	0
g_div4.Div4Whole_A	237252836	5255	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237252836	4602	0	0
T1	527319	12	0	0
T2	789853	95	0	0
T3	91260	0	0	0
T4	3469	0	0	0
T5	78436	0	0	0
T6	5609	0	0	0
T10	0	68	0	0
T17	1340	0	0	0
T18	3582	0	0	0
T19	38180	0	0	0
T20	1991	1	0	0
T34	0	3	0	0
T35	0	15	0	0
T61	0	5	0	0
T68	0	9	0	0
T77	0	2	0	0
T78	0	9	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237252836	5255	0	0
T1	527319	12	0	0
T2	789853	111	0	0
T3	91260	0	0	0
T4	3469	0	0	0
T5	78436	0	0	0
T6	5609	0	0	0
T10	0	77	0	0
T17	1340	0	0	0
T18	3582	0	0	0
T19	38180	0	0	0
T20	1991	1	0	0
T34	0	3	0	0
T35	0	15	0	0
T61	0	5	0	0
T68	0	11	0	0
T77	0	3	0	0
T78	0	6	0	0