Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	497838021	390	0	0
StatusRise_A	497838021	390	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497838021	390	0	0
T10	1337604	0	0	0
T11	827265	0	0	0
T31	4005	7	0	0
T32	0	8	0	0
T33	0	3	0	0
T68	5454	0	0	0
T77	3516	0	0	0
T78	7452	0	0	0
T79	3756	0	0	0
T80	3354	0	0	0
T106	6720	0	0	0
T139	3966	0	0	0
T148	0	13	0	0
T163	0	6	0	0
T164	0	13	0	0
T165	0	2	0	0
T166	0	15	0	0
T167	0	5	0	0
T168	0	14	0	0
T169	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497838021	390	0	0
T10	1337604	0	0	0
T11	827265	0	0	0
T31	4005	7	0	0
T32	0	8	0	0
T33	0	3	0	0
T68	5454	0	0	0
T77	3516	0	0	0
T78	7452	0	0	0
T79	3756	0	0	0
T80	3354	0	0	0
T106	6720	0	0	0
T139	3966	0	0	0
T148	0	13	0	0
T163	0	6	0	0
T164	0	13	0	0
T165	0	2	0	0
T166	0	15	0	0
T167	0	5	0	0
T168	0	14	0	0
T169	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	165946007	129	0	0
StatusRise_A	165946007	129	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165946007	129	0	0
T10	445868	0	0	0
T11	275755	0	0	0
T31	1335	2	0	0
T32	0	3	0	0
T33	0	1	0	0
T68	1818	0	0	0
T77	1172	0	0	0
T78	2484	0	0	0
T79	1252	0	0	0
T80	1118	0	0	0
T106	2240	0	0	0
T139	1322	0	0	0
T148	0	5	0	0
T163	0	1	0	0
T164	0	3	0	0
T165	0	1	0	0
T166	0	6	0	0
T167	0	2	0	0
T168	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165946007	129	0	0
T10	445868	0	0	0
T11	275755	0	0	0
T31	1335	2	0	0
T32	0	3	0	0
T33	0	1	0	0
T68	1818	0	0	0
T77	1172	0	0	0
T78	2484	0	0	0
T79	1252	0	0	0
T80	1118	0	0	0
T106	2240	0	0	0
T139	1322	0	0	0
T148	0	5	0	0
T163	0	1	0	0
T164	0	3	0	0
T165	0	1	0	0
T166	0	6	0	0
T167	0	2	0	0
T168	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	165946007	130	0	0
StatusRise_A	165946007	130	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165946007	130	0	0
T10	445868	0	0	0
T11	275755	0	0	0
T31	1335	2	0	0
T32	0	2	0	0
T33	0	1	0	0
T68	1818	0	0	0
T77	1172	0	0	0
T78	2484	0	0	0
T79	1252	0	0	0
T80	1118	0	0	0
T106	2240	0	0	0
T139	1322	0	0	0
T148	0	3	0	0
T163	0	2	0	0
T164	0	7	0	0
T166	0	4	0	0
T167	0	1	0	0
T168	0	4	0	0
T169	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165946007	130	0	0
T10	445868	0	0	0
T11	275755	0	0	0
T31	1335	2	0	0
T32	0	2	0	0
T33	0	1	0	0
T68	1818	0	0	0
T77	1172	0	0	0
T78	2484	0	0	0
T79	1252	0	0	0
T80	1118	0	0	0
T106	2240	0	0	0
T139	1322	0	0	0
T148	0	3	0	0
T163	0	2	0	0
T164	0	7	0	0
T166	0	4	0	0
T167	0	1	0	0
T168	0	4	0	0
T169	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	165946007	131	0	0
StatusRise_A	165946007	131	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165946007	131	0	0
T10	445868	0	0	0
T11	275755	0	0	0
T31	1335	3	0	0
T32	0	3	0	0
T33	0	1	0	0
T68	1818	0	0	0
T77	1172	0	0	0
T78	2484	0	0	0
T79	1252	0	0	0
T80	1118	0	0	0
T106	2240	0	0	0
T139	1322	0	0	0
T148	0	5	0	0
T163	0	3	0	0
T164	0	3	0	0
T165	0	1	0	0
T166	0	5	0	0
T167	0	2	0	0
T168	0	6	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165946007	131	0	0
T10	445868	0	0	0
T11	275755	0	0	0
T31	1335	3	0	0
T32	0	3	0	0
T33	0	1	0	0
T68	1818	0	0	0
T77	1172	0	0	0
T78	2484	0	0	0
T79	1252	0	0	0
T80	1118	0	0	0
T106	2240	0	0	0
T139	1322	0	0	0
T148	0	5	0	0
T163	0	3	0	0
T164	0	3	0	0
T165	0	1	0	0
T166	0	5	0	0
T167	0	2	0	0
T168	0	6	0	0