Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T6,T5
1	1	Covered	T1,T6,T5

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	47920	0	0
CgEnOn_A	2147483647	38865	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	47920	0	0
T1	1393568	141	0	0
T2	2810419	598	0	0
T3	1171947	3	0	0
T4	81137	9	0	0
T5	1120872	3	0	0
T6	67058	7	0	0
T10	2090071	60	0	0
T11	3002305	0	0	0
T17	16195	4	0	0
T18	43079	7	0	0
T19	574111	3	0	0
T20	25812	6	0	0
T31	5789	12	0	0
T32	0	10	0	0
T33	0	5	0	0
T35	3684	0	0	0
T68	32031	0	0	0
T77	9756	0	0	0
T78	10581	0	0	0
T79	10459	0	0	0
T80	8489	0	0	0
T106	9992	0	0	0
T139	10522	0	0	0
T148	0	15	0	0
T163	0	10	0	0
T164	0	35	0	0
T166	0	20	0	0
T167	0	5	0	0
T168	0	20	0	0
T169	0	25	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	38865	0	0
T1	2004514	117	0	0
T2	2810419	565	0	0
T3	1171947	0	0	0
T4	88486	0	0	0
T5	1225298	0	0	0
T6	72733	4	0	0
T10	2090071	261	0	0
T11	3139325	237	0	0
T13	0	13	0	0
T17	17567	1	0	0
T18	46728	4	0	0
T19	574111	0	0	0
T20	25812	0	0	0
T31	5789	18	0	0
T32	0	10	0	0
T33	0	5	0	0
T68	32031	0	0	0
T77	10882	0	0	0
T78	11773	0	0	0
T79	11685	0	0	0
T80	9483	0	0	0
T106	11123	0	0	0
T107	0	3	0	0
T109	0	3	0	0
T139	11743	0	0	0
T148	0	15	0	0
T152	0	3	0	0
T163	0	10	0	0
T164	0	35	0	0
T166	0	20	0	0
T167	0	5	0	0
T168	0	20	0	0
T169	0	25	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Covered	T1,T6,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	237252428	135	0	0
CgEnOn_A	237252428	135	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237252428	135	0	0
T10	209602	0	0	0
T11	135075	0	0	0
T31	552	2	0	0
T32	0	2	0	0
T33	0	1	0	0
T68	3547	0	0	0
T77	1126	0	0	0
T78	1293	0	0	0
T79	1159	0	0	0
T80	941	0	0	0
T106	1207	0	0	0
T139	1197	0	0	0
T148	0	3	0	0
T163	0	2	0	0
T164	0	7	0	0
T166	0	4	0	0
T167	0	1	0	0
T168	0	4	0	0
T169	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237252428	135	0	0
T10	209602	0	0	0
T11	135075	0	0	0
T31	552	2	0	0
T32	0	2	0	0
T33	0	1	0	0
T68	3547	0	0	0
T77	1126	0	0	0
T78	1293	0	0	0
T79	1159	0	0	0
T80	941	0	0	0
T106	1207	0	0	0
T139	1197	0	0	0
T148	0	3	0	0
T163	0	2	0	0
T164	0	7	0	0
T166	0	4	0	0
T167	0	1	0	0
T168	0	4	0	0
T169	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Covered	T1,T6,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	118625572	135	0	0
CgEnOn_A	118625572	135	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118625572	135	0	0
T10	104800	0	0	0
T11	675372	0	0	0
T31	276	2	0	0
T32	0	2	0	0
T33	0	1	0	0
T68	1772	0	0	0
T77	562	0	0	0
T78	645	0	0	0
T79	580	0	0	0
T80	471	0	0	0
T106	603	0	0	0
T139	599	0	0	0
T148	0	3	0	0
T163	0	2	0	0
T164	0	7	0	0
T166	0	4	0	0
T167	0	1	0	0
T168	0	4	0	0
T169	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118625572	135	0	0
T10	104800	0	0	0
T11	675372	0	0	0
T31	276	2	0	0
T32	0	2	0	0
T33	0	1	0	0
T68	1772	0	0	0
T77	562	0	0	0
T78	645	0	0	0
T79	580	0	0	0
T80	471	0	0	0
T106	603	0	0	0
T139	599	0	0	0
T148	0	3	0	0
T163	0	2	0	0
T164	0	7	0	0
T166	0	4	0	0
T167	0	1	0	0
T168	0	4	0	0
T169	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Covered	T1,T6,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	118625572	135	0	0
CgEnOn_A	118625572	135	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118625572	135	0	0
T10	104800	0	0	0
T11	675372	0	0	0
T31	276	2	0	0
T32	0	2	0	0
T33	0	1	0	0
T68	1772	0	0	0
T77	562	0	0	0
T78	645	0	0	0
T79	580	0	0	0
T80	471	0	0	0
T106	603	0	0	0
T139	599	0	0	0
T148	0	3	0	0
T163	0	2	0	0
T164	0	7	0	0
T166	0	4	0	0
T167	0	1	0	0
T168	0	4	0	0
T169	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118625572	135	0	0
T10	104800	0	0	0
T11	675372	0	0	0
T31	276	2	0	0
T32	0	2	0	0
T33	0	1	0	0
T68	1772	0	0	0
T77	562	0	0	0
T78	645	0	0	0
T79	580	0	0	0
T80	471	0	0	0
T106	603	0	0	0
T139	599	0	0	0
T148	0	3	0	0
T163	0	2	0	0
T164	0	7	0	0
T166	0	4	0	0
T167	0	1	0	0
T168	0	4	0	0
T169	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Covered	T1,T6,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	118625572	135	0	0
CgEnOn_A	118625572	135	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118625572	135	0	0
T10	104800	0	0	0
T11	675372	0	0	0
T31	276	2	0	0
T32	0	2	0	0
T33	0	1	0	0
T68	1772	0	0	0
T77	562	0	0	0
T78	645	0	0	0
T79	580	0	0	0
T80	471	0	0	0
T106	603	0	0	0
T139	599	0	0	0
T148	0	3	0	0
T163	0	2	0	0
T164	0	7	0	0
T166	0	4	0	0
T167	0	1	0	0
T168	0	4	0	0
T169	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118625572	135	0	0
T10	104800	0	0	0
T11	675372	0	0	0
T31	276	2	0	0
T32	0	2	0	0
T33	0	1	0	0
T68	1772	0	0	0
T77	562	0	0	0
T78	645	0	0	0
T79	580	0	0	0
T80	471	0	0	0
T106	603	0	0	0
T139	599	0	0	0
T148	0	3	0	0
T163	0	2	0	0
T164	0	7	0	0
T166	0	4	0	0
T167	0	1	0	0
T168	0	4	0	0
T169	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Covered	T1,T6,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	473979546	135	0	0
CgEnOn_A	473979546	131	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473979546	135	0	0
T10	421158	0	0	0
T11	270206	0	0	0
T31	1237	2	0	0
T32	0	2	0	0
T33	0	1	0	0
T68	6465	0	0	0
T77	2252	0	0	0
T78	2385	0	0	0
T79	2452	0	0	0
T80	1989	0	0	0
T106	2262	0	0	0
T139	2442	0	0	0
T148	0	3	0	0
T163	0	2	0	0
T164	0	7	0	0
T166	0	4	0	0
T167	0	1	0	0
T168	0	4	0	0
T169	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473979546	131	0	0
T10	421158	0	0	0
T11	270206	0	0	0
T31	1237	2	0	0
T32	0	2	0	0
T33	0	1	0	0
T68	6465	0	0	0
T77	2252	0	0	0
T78	2385	0	0	0
T79	2452	0	0	0
T80	1989	0	0	0
T106	2262	0	0	0
T139	2442	0	0	0
T148	0	3	0	0
T163	0	2	0	0
T164	0	7	0	0
T166	0	4	0	0
T167	0	1	0	0
T168	0	4	0	0
T169	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Covered	T1,T6,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	504798337	133	0	0
CgEnOn_A	504798337	130	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504798337	133	0	0
T10	462121	0	0	0
T11	285454	0	0	0
T31	1280	2	0	0
T32	0	3	0	0
T33	0	1	0	0
T68	6735	0	0	0
T77	2346	0	0	0
T78	2484	0	0	0
T79	2554	0	0	0
T80	2073	0	0	0
T106	2357	0	0	0
T139	2543	0	0	0
T148	0	5	0	0
T163	0	1	0	0
T164	0	3	0	0
T165	0	1	0	0
T166	0	6	0	0
T167	0	2	0	0
T168	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504798337	130	0	0
T10	462121	0	0	0
T11	285454	0	0	0
T31	1280	2	0	0
T32	0	3	0	0
T33	0	1	0	0
T68	6735	0	0	0
T77	2346	0	0	0
T78	2484	0	0	0
T79	2554	0	0	0
T80	2073	0	0	0
T106	2357	0	0	0
T139	2543	0	0	0
T148	0	5	0	0
T163	0	1	0	0
T164	0	3	0	0
T165	0	1	0	0
T166	0	6	0	0
T167	0	2	0	0
T168	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Covered	T1,T6,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	504798337	133	0	0
CgEnOn_A	504798337	130	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504798337	133	0	0
T10	462121	0	0	0
T11	285454	0	0	0
T31	1280	2	0	0
T32	0	3	0	0
T33	0	1	0	0
T68	6735	0	0	0
T77	2346	0	0	0
T78	2484	0	0	0
T79	2554	0	0	0
T80	2073	0	0	0
T106	2357	0	0	0
T139	2543	0	0	0
T148	0	5	0	0
T163	0	1	0	0
T164	0	3	0	0
T165	0	1	0	0
T166	0	6	0	0
T167	0	2	0	0
T168	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504798337	130	0	0
T10	462121	0	0	0
T11	285454	0	0	0
T31	1280	2	0	0
T32	0	3	0	0
T33	0	1	0	0
T68	6735	0	0	0
T77	2346	0	0	0
T78	2484	0	0	0
T79	2554	0	0	0
T80	2073	0	0	0
T106	2357	0	0	0
T139	2543	0	0	0
T148	0	5	0	0
T163	0	1	0	0
T164	0	3	0	0
T165	0	1	0	0
T166	0	6	0	0
T167	0	2	0	0
T168	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Covered	T1,T6,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	242470804	135	0	0
CgEnOn_A	242470804	131	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	242470804	135	0	0
T2	800326	1	0	0
T3	91330	0	0	0
T10	220669	0	0	0
T19	49755	0	0	0
T20	2015	0	0	0
T31	612	3	0	0
T32	0	3	0	0
T33	0	1	0	0
T34	1112	0	0	0
T35	3684	0	0	0
T61	1227	0	0	0
T68	3233	0	0	0
T148	0	5	0	0
T163	0	3	0	0
T164	0	3	0	0
T165	0	1	0	0
T166	0	5	0	0
T167	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	242470804	131	0	0
T10	220669	0	0	0
T11	137020	0	0	0
T31	612	3	0	0
T32	0	3	0	0
T33	0	1	0	0
T68	3233	0	0	0
T77	1126	0	0	0
T78	1192	0	0	0
T79	1226	0	0	0
T80	994	0	0	0
T106	1131	0	0	0
T139	1221	0	0	0
T148	0	5	0	0
T163	0	3	0	0
T164	0	3	0	0
T165	0	1	0	0
T166	0	5	0	0
T167	0	2	0	0
T168	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T33
1	0	Covered	T1,T6,T5
1	1	Covered	T1,T6,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	118625572	7451	0	0
CgEnOn_A	118625572	5196	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118625572	7451	0	0
T1	263658	44	0	0
T2	394925	162	0	0
T3	45630	1	0	0
T4	1735	3	0	0
T5	39218	1	0	0
T6	2804	1	0	0
T17	670	1	0	0
T18	1791	2	0	0
T19	19090	1	0	0
T20	995	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118625572	5196	0	0
T1	263658	36	0	0
T2	394925	151	0	0
T3	45630	0	0	0
T4	1735	0	0	0
T5	39218	0	0	0
T6	2804	0	0	0
T10	0	68	0	0
T11	0	59	0	0
T13	0	1	0	0
T17	670	0	0	0
T18	1791	1	0	0
T19	19090	0	0	0
T20	995	0	0	0
T31	0	2	0	0
T107	0	1	0	0
T109	0	1	0	0
T152	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T33
1	0	Covered	T1,T6,T5
1	1	Covered	T1,T6,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	237252428	7455	0	0
CgEnOn_A	237252428	5200	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237252428	7455	0	0
T1	527319	44	0	0
T2	789853	170	0	0
T3	91259	1	0	0
T4	3469	3	0	0
T5	78436	1	0	0
T6	5608	1	0	0
T17	1340	1	0	0
T18	3582	2	0	0
T19	38180	1	0	0
T20	1990	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237252428	5200	0	0
T1	527319	36	0	0
T2	789853	159	0	0
T3	91259	0	0	0
T4	3469	0	0	0
T5	78436	0	0	0
T6	5608	0	0	0
T10	0	65	0	0
T11	0	62	0	0
T13	0	1	0	0
T17	1340	0	0	0
T18	3582	1	0	0
T19	38180	0	0	0
T20	1990	0	0	0
T31	0	2	0	0
T107	0	1	0	0
T109	0	1	0	0
T152	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T33
1	0	Covered	T1,T6,T5
1	1	Covered	T1,T6,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	473979546	7509	0	0
CgEnOn_A	473979546	5250	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473979546	7509	0	0
T1	105479	42	0	0
T2	157923	160	0	0
T3	182652	1	0	0
T4	14697	3	0	0
T5	157006	1	0	0
T6	11350	1	0	0
T17	2745	1	0	0
T18	7298	2	0	0
T19	76466	1	0	0
T20	4028	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473979546	5250	0	0
T1	105479	34	0	0
T2	157923	149	0	0
T3	182652	0	0	0
T4	14697	0	0	0
T5	157006	0	0	0
T6	11350	0	0	0
T10	0	68	0	0
T11	0	61	0	0
T13	0	1	0	0
T17	2745	0	0	0
T18	7298	1	0	0
T19	76466	0	0	0
T20	4028	0	0	0
T31	0	2	0	0
T107	0	1	0	0
T109	0	1	0	0
T152	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T33
1	0	Covered	T1,T6,T5
1	1	Covered	T1,T6,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	242470804	7490	0	0
CgEnOn_A	242470804	5230	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	242470804	7490	0	0
T1	610946	42	0	0
T2	800326	162	0	0
T3	91330	1	0	0
T4	7349	3	0	0
T5	104426	1	0	0
T6	5675	1	0	0
T17	1372	1	0	0
T18	3649	2	0	0
T19	49755	1	0	0
T20	2015	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	242470804	5230	0	0
T1	610946	34	0	0
T2	800326	151	0	0
T3	91330	0	0	0
T4	7349	0	0	0
T5	104426	0	0	0
T6	5675	0	0	0
T10	0	65	0	0
T11	0	59	0	0
T13	0	1	0	0
T17	1372	0	0	0
T18	3649	1	0	0
T19	49755	0	0	0
T20	2015	0	0	0
T31	0	3	0	0
T107	0	1	0	0
T109	0	1	0	0
T152	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T6,T17
1	1	Covered	T1,T6,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	504798337	4199	0	0
CgEnOn_A	504798337	4196	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504798337	4199	0	0
T1	124278	11	0	0
T2	166848	106	0	0
T3	190269	0	0	0
T4	15309	0	0	0
T5	211553	0	0	0
T6	11824	4	0	0
T10	0	60	0	0
T11	0	55	0	0
T13	0	10	0	0
T17	2860	1	0	0
T18	7602	1	0	0
T19	97655	0	0	0
T20	4196	0	0	0
T31	0	2	0	0
T79	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504798337	4196	0	0
T1	124278	11	0	0
T2	166848	106	0	0
T3	190269	0	0	0
T4	15309	0	0	0
T5	211553	0	0	0
T6	11824	4	0	0
T10	0	60	0	0
T11	0	55	0	0
T13	0	10	0	0
T17	2860	1	0	0
T18	7602	1	0	0
T19	97655	0	0	0
T20	4196	0	0	0
T31	0	2	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T6,T18
1	1	Covered	T1,T6,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	504798337	4231	0	0
CgEnOn_A	504798337	4228	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504798337	4231	0	0
T1	124278	14	0	0
T2	166848	110	0	0
T3	190269	0	0	0
T4	15309	0	0	0
T5	211553	0	0	0
T6	11824	11	0	0
T10	0	57	0	0
T11	0	54	0	0
T13	0	9	0	0
T17	2860	0	0	0
T18	7602	1	0	0
T19	97655	0	0	0
T20	4196	0	0	0
T31	0	2	0	0
T107	0	1	0	0
T108	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504798337	4228	0	0
T1	124278	14	0	0
T2	166848	110	0	0
T3	190269	0	0	0
T4	15309	0	0	0
T5	211553	0	0	0
T6	11824	11	0	0
T10	0	57	0	0
T11	0	54	0	0
T13	0	9	0	0
T17	2860	0	0	0
T18	7602	1	0	0
T19	97655	0	0	0
T20	4196	0	0	0
T31	0	2	0	0
T107	0	1	0	0
T108	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T6,T17
1	1	Covered	T1,T6,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	504798337	4223	0	0
CgEnOn_A	504798337	4220	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504798337	4223	0	0
T1	124278	16	0	0
T2	166848	105	0	0
T3	190269	0	0	0
T4	15309	0	0	0
T5	211553	0	0	0
T6	11824	12	0	0
T10	0	53	0	0
T11	0	47	0	0
T13	0	9	0	0
T17	2860	1	0	0
T18	7602	1	0	0
T19	97655	0	0	0
T20	4196	0	0	0
T31	0	2	0	0
T79	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504798337	4220	0	0
T1	124278	16	0	0
T2	166848	105	0	0
T3	190269	0	0	0
T4	15309	0	0	0
T5	211553	0	0	0
T6	11824	12	0	0
T10	0	53	0	0
T11	0	47	0	0
T13	0	9	0	0
T17	2860	1	0	0
T18	7602	1	0	0
T19	97655	0	0	0
T20	4196	0	0	0
T31	0	2	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T6,T17
1	1	Covered	T1,T6,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	504798337	4286	0	0
CgEnOn_A	504798337	4283	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504798337	4286	0	0
T1	124278	9	0	0
T2	166848	102	0	0
T3	190269	0	0	0
T4	15309	0	0	0
T5	211553	0	0	0
T6	11824	10	0	0
T10	0	56	0	0
T11	0	54	0	0
T13	0	10	0	0
T17	2860	3	0	0
T18	7602	1	0	0
T19	97655	0	0	0
T20	4196	0	0	0
T31	0	2	0	0
T79	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504798337	4283	0	0
T1	124278	9	0	0
T2	166848	102	0	0
T3	190269	0	0	0
T4	15309	0	0	0
T5	211553	0	0	0
T6	11824	10	0	0
T10	0	56	0	0
T11	0	54	0	0
T13	0	10	0	0
T17	2860	3	0	0
T18	7602	1	0	0
T19	97655	0	0	0
T20	4196	0	0	0
T31	0	2	0	0
T79	0	1	0	0