Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	605164	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3350980

1

T6

30

T7

9

T1

200

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	973441	1			T6	42		T1	59		T15	6
values[0x0]	1371341	1			T6	9		T7	17		T1	178
values[0x1]	1611362	1			T6	30		T7	14		T1	181

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	338214	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3617930

1

T6

44

T7

9

T1

264

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16655	1			T1	3		T2	3		T17	3
valid_sources[0x01]	15212	1			T17	3		T158	2		T29	2
valid_sources[0x02]	16291	1			T1	6		T5	10		T17	7
valid_sources[0x03]	14810	1			T7	1		T1	1		T2	5
valid_sources[0x04]	15643	1			T4	2		T5	2		T2	4
valid_sources[0x05]	15888	1			T7	1		T1	1		T4	2
valid_sources[0x06]	15213	1			T1	2		T5	1		T2	1
valid_sources[0x07]	16884	1			T4	1		T2	8		T17	1
valid_sources[0x08]	14752	1			T1	1		T2	1		T17	6
valid_sources[0x09]	16825	1			T1	2		T2	5		T28	2
valid_sources[0x0a]	15193	1			T1	1		T5	2		T2	2
valid_sources[0x0b]	15859	1			T1	7		T4	8		T5	2
valid_sources[0x0c]	15179	1			T4	5		T2	3		T17	3
valid_sources[0x0d]	14839	1			T1	1		T2	2		T28	10
valid_sources[0x0e]	13941	1			T1	3		T5	9		T17	8
valid_sources[0x0f]	16277	1			T5	7		T2	2		T17	5
valid_sources[0x10]	14692	1			T1	2		T5	2		T17	1
valid_sources[0x11]	15104	1			T1	2		T17	5		T29	1
valid_sources[0x12]	15066	1			T1	3		T5	1		T2	3
valid_sources[0x13]	17430	1			T1	1		T17	9		T28	1
valid_sources[0x14]	15252	1			T1	3		T4	1		T5	1
valid_sources[0x15]	14378	1			T1	1		T5	1		T2	2
valid_sources[0x16]	15420	1			T1	1		T2	3		T17	2
valid_sources[0x17]	13907	1			T1	3		T5	6		T128	1
valid_sources[0x18]	15965	1			T4	4		T5	3		T17	1
valid_sources[0x19]	15211	1			T7	1		T1	1		T4	2
valid_sources[0x1a]	14982	1			T1	4		T5	1		T17	1
valid_sources[0x1b]	16598	1			T1	2		T2	5		T17	5
valid_sources[0x1c]	13133	1			T1	1		T4	1		T5	1
valid_sources[0x1d]	16267	1			T1	1		T4	1		T5	5
valid_sources[0x1e]	15234	1			T1	1		T5	3		T28	5
valid_sources[0x1f]	14096	1			T1	3		T5	1		T29	2
valid_sources[0x20]	15266	1			T1	1		T5	7		T2	1
valid_sources[0x21]	14755	1			T1	4		T5	2		T17	2
valid_sources[0x22]	15819	1			T1	5		T5	1		T8	114
valid_sources[0x23]	16098	1			T5	3		T2	1		T17	5
valid_sources[0x24]	14976	1			T5	1		T2	1		T17	1
valid_sources[0x25]	14288	1			T5	1		T17	5		T28	2
valid_sources[0x26]	14750	1			T1	3		T2	1		T17	4
valid_sources[0x27]	14363	1			T28	1		T158	1		T29	2
valid_sources[0x28]	16674	1			T1	3		T4	1		T5	6
valid_sources[0x29]	16483	1			T1	2		T4	1		T5	1
valid_sources[0x2a]	14765	1			T5	9		T17	5		T28	4
valid_sources[0x2b]	16945	1			T1	1		T4	3		T2	1
valid_sources[0x2c]	14803	1			T1	2		T4	1		T28	1
valid_sources[0x2d]	16114	1			T4	2		T17	2		T158	1
valid_sources[0x2e]	13304	1			T1	3		T5	3		T2	1
valid_sources[0x2f]	16943	1			T7	1		T1	1		T5	2
valid_sources[0x30]	16959	1			T1	1		T5	4		T2	1
valid_sources[0x31]	15423	1			T1	1		T5	12		T17	1
valid_sources[0x32]	16121	1			T4	1		T5	3		T2	2
valid_sources[0x33]	14844	1			T1	2		T4	2		T2	2
valid_sources[0x34]	16271	1			T1	3		T2	4		T17	3
valid_sources[0x35]	17092	1			T1	1		T5	2		T2	1
valid_sources[0x36]	15033	1			T7	1		T4	2		T17	2
valid_sources[0x37]	14508	1			T1	7		T4	5		T5	2
valid_sources[0x38]	15108	1			T7	2		T1	4		T4	1
valid_sources[0x39]	15124	1			T1	3		T4	2		T5	3
valid_sources[0x3a]	14303	1			T1	4		T4	3		T5	3
valid_sources[0x3b]	16461	1			T1	4		T5	5		T2	1
valid_sources[0x3c]	15899	1			T1	2		T2	6		T28	1
valid_sources[0x3d]	13854	1			T1	2		T4	8		T5	7
valid_sources[0x3e]	16553	1			T1	3		T2	1		T17	1
valid_sources[0x3f]	15703	1			T5	4		T17	2		T28	14
valid_sources[0x40]	14532	1			T1	2		T5	6		T17	6
valid_sources[0x41]	14707	1			T1	2		T28	2		T8	172
valid_sources[0x42]	16376	1			T1	1		T4	2		T5	2
valid_sources[0x43]	15028	1			T1	1		T5	7		T2	3
valid_sources[0x44]	14640	1			T7	1		T1	2		T4	3
valid_sources[0x45]	14152	1			T6	5		T1	2		T5	4
valid_sources[0x46]	14646	1			T4	1		T5	6		T2	7
valid_sources[0x47]	19505	1			T4	3		T2	1		T17	9
valid_sources[0x48]	17222	1			T1	3		T5	1		T2	2
valid_sources[0x49]	16323	1			T1	1		T17	2		T29	5
valid_sources[0x4a]	14641	1			T7	2		T1	1		T4	1
valid_sources[0x4b]	16599	1			T1	1		T5	2		T2	2
valid_sources[0x4c]	14587	1			T1	5		T17	1		T32	7
valid_sources[0x4d]	13644	1			T1	2		T4	2		T5	2
valid_sources[0x4e]	17339	1			T4	2		T2	4		T17	2
valid_sources[0x4f]	15318	1			T1	3		T2	3		T74	1
valid_sources[0x50]	15007	1			T7	1		T1	2		T2	2
valid_sources[0x51]	16846	1			T4	2		T5	3		T2	11
valid_sources[0x52]	15264	1			T6	7		T1	2		T2	1
valid_sources[0x53]	15589	1			T17	9		T29	2		T22	4
valid_sources[0x54]	14912	1			T2	1		T17	5		T28	2
valid_sources[0x55]	14871	1			T1	2		T4	5		T5	1
valid_sources[0x56]	14427	1			T7	1		T1	1		T4	2
valid_sources[0x57]	16294	1			T1	2		T17	1		T40	2
valid_sources[0x58]	15739	1			T7	1		T1	5		T17	3
valid_sources[0x59]	14695	1			T1	1		T17	3		T28	2
valid_sources[0x5a]	15791	1			T1	2		T4	2		T5	1
valid_sources[0x5b]	14732	1			T5	4		T2	1		T17	5
valid_sources[0x5c]	15894	1			T1	2		T5	3		T2	4
valid_sources[0x5d]	14821	1			T6	7		T1	1		T5	2
valid_sources[0x5e]	14013	1			T1	1		T4	1		T5	1
valid_sources[0x5f]	15383	1			T1	1		T5	2		T2	1
valid_sources[0x60]	16426	1			T1	1		T4	1		T17	5
valid_sources[0x61]	15383	1			T1	1		T4	5		T17	6
valid_sources[0x62]	14621	1			T5	2		T17	1		T127	1
valid_sources[0x63]	16389	1			T1	1		T5	14		T2	3
valid_sources[0x64]	15576	1			T1	1		T4	4		T2	4
valid_sources[0x65]	15171	1			T1	3		T5	1		T17	2
valid_sources[0x66]	15133	1			T4	2		T2	3		T17	11
valid_sources[0x67]	16185	1			T1	1		T5	2		T2	8
valid_sources[0x68]	15141	1			T1	2		T15	6		T4	1
valid_sources[0x69]	16071	1			T1	1		T4	3		T5	15
valid_sources[0x6a]	13508	1			T1	1		T5	1		T2	5
valid_sources[0x6b]	16955	1			T1	4		T5	1		T2	2
valid_sources[0x6c]	14288	1			T5	3		T2	6		T17	4
valid_sources[0x6d]	15485	1			T2	2		T29	6		T8	101
valid_sources[0x6e]	14653	1			T6	8		T1	2		T5	3
valid_sources[0x6f]	17744	1			T17	2		T86	1		T128	1
valid_sources[0x70]	16389	1			T1	2		T5	1		T17	5
valid_sources[0x71]	16517	1			T6	4		T1	1		T2	5
valid_sources[0x72]	16890	1			T1	1		T5	9		T2	1
valid_sources[0x73]	13573	1			T1	3		T5	2		T2	4
valid_sources[0x74]	14510	1			T5	5		T2	1		T17	4
valid_sources[0x75]	14130	1			T7	1		T1	1		T17	2
valid_sources[0x76]	14362	1			T1	4		T2	4		T17	7
valid_sources[0x77]	15817	1			T5	3		T2	2		T17	3
valid_sources[0x78]	15673	1			T1	6		T17	3		T29	1
valid_sources[0x79]	15341	1			T1	1		T17	3		T28	4
valid_sources[0x7a]	15008	1			T5	2		T17	6		T29	2
valid_sources[0x7b]	14725	1			T1	3		T5	1		T2	2
valid_sources[0x7c]	17266	1			T7	2		T1	2		T5	3
valid_sources[0x7d]	14614	1			T1	2		T4	3		T5	4
valid_sources[0x7e]	15084	1			T1	3		T5	2		T2	3
valid_sources[0x7f]	15558	1			T1	6		T4	3		T5	2
valid_sources[0x80]	15085	1			T1	4		T4	5		T17	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

846589

1

T6

19

T1

26

T15

4

values[0x0]

all_enables

biggest_size

1275883

1

T6

2

T7

5

T1

105

values[0x1]

all_enables

biggest_size

1228508

1

T6

9

T7

4

T1

69