Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T4
0	1	Covered	T7,T158,T8
1	0	Covered	T6,T7,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T4
1	0	Covered	T16,T24,T25
1	1	Covered	T6,T7,T1

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1068279577	15515	0	0
GateOpen_A	1068279577	21443	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068279577	15515	0	0
T1	433543	0	0	0
T2	539383	0	0	0
T4	61353	0	0	0
T5	152138	0	0	0
T6	10865	4	0	0
T7	9343	32	0	0
T15	10716	0	0	0
T16	2866	12	0	0
T17	224312	0	0	0
T18	5291	0	0	0
T24	0	14	0	0
T25	0	19	0	0
T26	0	22	0	0
T39	0	4	0	0
T42	0	4	0	0
T157	0	20	0	0
T158	0	42	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068279577	21443	0	0
T1	433543	0	0	0
T2	539383	0	0	0
T4	61353	20	0	0
T5	152138	56	0	0
T6	10865	8	0	0
T7	9343	36	0	0
T15	10716	4	0	0
T16	2866	16	0	0
T17	224312	72	0	0
T18	5291	0	0	0
T20	0	4	0	0
T24	0	18	0	0
T25	0	23	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T4
0	1	Covered	T7,T158,T8
1	0	Covered	T6,T7,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T4
1	0	Covered	T16,T24,T25
1	1	Covered	T6,T7,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	118474571	3704	0	0
GateOpen_A	118474571	5185	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118474571	3704	0	0
T1	48163	0	0	0
T2	59916	0	0	0
T4	4960	0	0	0
T5	9937	0	0	0
T6	1199	1	0	0
T7	1023	7	0	0
T15	1218	0	0	0
T16	296	3	0	0
T17	16431	0	0	0
T18	641	0	0	0
T24	0	4	0	0
T25	0	5	0	0
T26	0	6	0	0
T39	0	1	0	0
T42	0	1	0	0
T157	0	5	0	0
T158	0	12	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118474571	5185	0	0
T1	48163	0	0	0
T2	59916	0	0	0
T4	4960	5	0	0
T5	9937	14	0	0
T6	1199	2	0	0
T7	1023	8	0	0
T15	1218	1	0	0
T16	296	4	0	0
T17	16431	18	0	0
T18	641	0	0	0
T20	0	1	0	0
T24	0	5	0	0
T25	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T4
0	1	Covered	T7,T158,T8
1	0	Covered	T6,T7,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T4
1	0	Covered	T16,T24,T25
1	1	Covered	T6,T7,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	236950022	3930	0	0
GateOpen_A	236950022	5411	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236950022	3930	0	0
T1	96325	0	0	0
T2	119831	0	0	0
T4	9919	0	0	0
T5	19873	0	0	0
T6	2397	1	0	0
T7	2045	8	0	0
T15	2435	0	0	0
T16	592	3	0	0
T17	32859	0	0	0
T18	1285	0	0	0
T24	0	4	0	0
T25	0	5	0	0
T26	0	6	0	0
T39	0	1	0	0
T42	0	1	0	0
T157	0	5	0	0
T158	0	10	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236950022	5411	0	0
T1	96325	0	0	0
T2	119831	0	0	0
T4	9919	5	0	0
T5	19873	14	0	0
T6	2397	2	0	0
T7	2045	9	0	0
T15	2435	1	0	0
T16	592	4	0	0
T17	32859	18	0	0
T18	1285	0	0	0
T20	0	1	0	0
T24	0	5	0	0
T25	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T4
0	1	Covered	T7,T158,T8
1	0	Covered	T6,T7,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T4
1	0	Covered	T16,T24,T25
1	1	Covered	T6,T7,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	471663159	3955	0	0
GateOpen_A	471663159	5438	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471663159	3955	0	0
T1	192700	0	0	0
T2	239754	0	0	0
T4	30982	0	0	0
T5	81551	0	0	0
T6	4846	1	0	0
T7	4183	9	0	0
T15	4709	0	0	0
T16	1305	3	0	0
T17	116680	0	0	0
T18	2243	0	0	0
T24	0	4	0	0
T25	0	5	0	0
T26	0	6	0	0
T39	0	1	0	0
T42	0	1	0	0
T157	0	5	0	0
T158	0	11	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471663159	5438	0	0
T1	192700	0	0	0
T2	239754	0	0	0
T4	30982	5	0	0
T5	81551	14	0	0
T6	4846	2	0	0
T7	4183	10	0	0
T15	4709	1	0	0
T16	1305	4	0	0
T17	116680	18	0	0
T18	2243	0	0	0
T20	0	1	0	0
T24	0	5	0	0
T25	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T4
0	1	Covered	T7,T158,T8
1	0	Covered	T6,T7,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T4
1	0	Covered	T16,T24,T25
1	1	Covered	T6,T7,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	241191825	3926	0	0
GateOpen_A	241191825	5409	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241191825	3926	0	0
T1	96355	0	0	0
T2	119882	0	0	0
T4	15492	0	0	0
T5	40777	0	0	0
T6	2423	1	0	0
T7	2092	8	0	0
T15	2354	0	0	0
T16	673	3	0	0
T17	58342	0	0	0
T18	1122	0	0	0
T24	0	2	0	0
T25	0	4	0	0
T26	0	4	0	0
T39	0	1	0	0
T42	0	1	0	0
T157	0	5	0	0
T158	0	9	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241191825	5409	0	0
T1	96355	0	0	0
T2	119882	0	0	0
T4	15492	5	0	0
T5	40777	14	0	0
T6	2423	2	0	0
T7	2092	9	0	0
T15	2354	1	0	0
T16	673	4	0	0
T17	58342	18	0	0
T18	1122	0	0	0
T20	0	1	0	0
T24	0	3	0	0
T25	0	5	0	0