Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	765259495	77133	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	765259495	77133	0	0
T1	632320	416	0	0
T2	224770	179	0	0
T3	0	115	0	0
T4	138775	0	0	0
T5	212375	0	0	0
T8	0	955	0	0
T9	0	1047	0	0
T10	0	1608	0	0
T11	0	118	0	0
T12	0	1448	0	0
T13	0	194	0	0
T14	0	606	0	0
T15	6125	0	0	0
T16	7225	0	0	0
T17	121540	0	0	0
T18	11680	0	0	0
T19	8885	0	0	0
T20	11345	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	153051899	11371	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153051899	11371	0	0
T1	126464	60	0	0
T2	44954	30	0	0
T3	0	17	0	0
T4	27755	0	0	0
T5	42475	0	0	0
T8	0	152	0	0
T9	0	136	0	0
T10	0	237	0	0
T11	0	20	0	0
T12	0	186	0	0
T13	0	35	0	0
T14	0	96	0	0
T15	1225	0	0	0
T16	1445	0	0	0
T17	24308	0	0	0
T18	2336	0	0	0
T19	1777	0	0	0
T20	2269	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	153051899	11144	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153051899	11144	0	0
T1	126464	57	0	0
T2	44954	30	0	0
T3	0	17	0	0
T4	27755	0	0	0
T5	42475	0	0	0
T8	0	149	0	0
T9	0	135	0	0
T10	0	198	0	0
T11	0	20	0	0
T12	0	184	0	0
T13	0	35	0	0
T14	0	97	0	0
T15	1225	0	0	0
T16	1445	0	0	0
T17	24308	0	0	0
T18	2336	0	0	0
T19	1777	0	0	0
T20	2269	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	153051899	15612	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153051899	15612	0	0
T1	126464	83	0	0
T2	44954	36	0	0
T3	0	23	0	0
T4	27755	0	0	0
T5	42475	0	0	0
T8	0	191	0	0
T9	0	215	0	0
T10	0	319	0	0
T11	0	25	0	0
T12	0	293	0	0
T13	0	38	0	0
T14	0	122	0	0
T15	1225	0	0	0
T16	1445	0	0	0
T17	24308	0	0	0
T18	2336	0	0	0
T19	1777	0	0	0
T20	2269	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	153051899	15463	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153051899	15463	0	0
T1	126464	82	0	0
T2	44954	36	0	0
T3	0	23	0	0
T4	27755	0	0	0
T5	42475	0	0	0
T8	0	196	0	0
T9	0	211	0	0
T10	0	325	0	0
T11	0	23	0	0
T12	0	297	0	0
T13	0	37	0	0
T14	0	122	0	0
T15	1225	0	0	0
T16	1445	0	0	0
T17	24308	0	0	0
T18	2336	0	0	0
T19	1777	0	0	0
T20	2269	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	153051899	23543	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153051899	23543	0	0
T1	126464	134	0	0
T2	44954	47	0	0
T3	0	35	0	0
T4	27755	0	0	0
T5	42475	0	0	0
T8	0	267	0	0
T9	0	350	0	0
T10	0	529	0	0
T11	0	30	0	0
T12	0	488	0	0
T13	0	49	0	0
T14	0	169	0	0
T15	1225	0	0	0
T16	1445	0	0	0
T17	24308	0	0	0
T18	2336	0	0	0
T19	1777	0	0	0
T20	2269	0	0	0