Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=1,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=6,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Module :
prim_mubi4_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T1 |
1 | Covered | T6,T7,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T1 |
1 | Covered | T6,T7,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T1 |
1 | Covered | T6,T7,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T1 |
1 | Covered | T6,T7,T1 |
Branch Coverage for Module :
prim_mubi4_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T1 |
0 |
Covered |
T6,T7,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T1 |
0 |
Covered |
T6,T7,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T1 |
0 |
Covered |
T6,T7,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T1 |
0 |
Covered |
T6,T7,T1 |
Assert Coverage for Module :
prim_mubi4_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22540 |
22540 |
0 |
0 |
T1 |
28 |
28 |
0 |
0 |
T2 |
28 |
28 |
0 |
0 |
T4 |
28 |
28 |
0 |
0 |
T5 |
28 |
28 |
0 |
0 |
T6 |
28 |
28 |
0 |
0 |
T7 |
28 |
28 |
0 |
0 |
T15 |
28 |
28 |
0 |
0 |
T16 |
28 |
28 |
0 |
0 |
T17 |
28 |
28 |
0 |
0 |
T18 |
28 |
28 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
4203361 |
4199970 |
0 |
0 |
T2 |
3656250 |
3654407 |
0 |
0 |
T4 |
771371 |
149767 |
0 |
0 |
T5 |
1592885 |
224402 |
0 |
0 |
T6 |
78072 |
76055 |
0 |
0 |
T7 |
67976 |
66167 |
0 |
0 |
T15 |
76716 |
74809 |
0 |
0 |
T16 |
36738 |
31010 |
0 |
0 |
T17 |
1775209 |
408621 |
0 |
0 |
T18 |
61260 |
57428 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
918311394 |
905265732 |
0 |
14490 |
T1 |
758784 |
758076 |
0 |
18 |
T2 |
269724 |
269556 |
0 |
18 |
T4 |
166530 |
20658 |
0 |
18 |
T5 |
254850 |
17304 |
0 |
18 |
T6 |
7260 |
7026 |
0 |
18 |
T7 |
6528 |
6324 |
0 |
18 |
T15 |
7350 |
7128 |
0 |
18 |
T16 |
8670 |
7254 |
0 |
18 |
T17 |
145848 |
19254 |
0 |
18 |
T18 |
14016 |
13068 |
0 |
18 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
16905 |
T1 |
1248572 |
1247409 |
0 |
21 |
T2 |
1328666 |
1327900 |
0 |
21 |
T4 |
215588 |
26735 |
0 |
21 |
T5 |
506300 |
34590 |
0 |
21 |
T6 |
27454 |
26596 |
0 |
21 |
T7 |
23790 |
23078 |
0 |
21 |
T15 |
26778 |
25990 |
0 |
21 |
T16 |
9678 |
7997 |
0 |
21 |
T17 |
651476 |
87145 |
0 |
21 |
T18 |
16259 |
15159 |
0 |
21 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
204933 |
0 |
0 |
T1 |
802944 |
4 |
0 |
0 |
T2 |
1328666 |
4 |
0 |
0 |
T4 |
215588 |
24 |
0 |
0 |
T5 |
506300 |
56 |
0 |
0 |
T6 |
20188 |
16 |
0 |
0 |
T7 |
17432 |
62 |
0 |
0 |
T15 |
26778 |
75 |
0 |
0 |
T16 |
9678 |
34 |
0 |
0 |
T17 |
651476 |
76 |
0 |
0 |
T18 |
16259 |
262 |
0 |
0 |
T19 |
5331 |
0 |
0 |
0 |
T20 |
13617 |
133 |
0 |
0 |
T24 |
4545 |
0 |
0 |
0 |
T40 |
0 |
88 |
0 |
0 |
T41 |
0 |
53 |
0 |
0 |
T74 |
0 |
107 |
0 |
0 |
T86 |
0 |
81 |
0 |
0 |
T127 |
0 |
35 |
0 |
0 |
T128 |
0 |
93 |
0 |
0 |
T129 |
0 |
78 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
2196005 |
2194446 |
0 |
0 |
T2 |
2057860 |
2056912 |
0 |
0 |
T4 |
389253 |
102140 |
0 |
0 |
T5 |
831735 |
171858 |
0 |
0 |
T6 |
43358 |
42394 |
0 |
0 |
T7 |
37658 |
36726 |
0 |
0 |
T15 |
42588 |
41652 |
0 |
0 |
T16 |
18390 |
15720 |
0 |
0 |
T17 |
977885 |
301337 |
0 |
0 |
T18 |
30985 |
29162 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T1 |
1 | Covered | T15,T18,T20 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T1 |
1 | Covered | T15,T18,T20 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T1 |
1 | Covered | T15,T18,T20 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T1 |
1 | Covered | T15,T18,T20 |
Branch Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T15,T18,T20 |
0 |
Covered |
T6,T7,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T15,T18,T20 |
0 |
Covered |
T6,T7,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T15,T18,T20 |
0 |
Covered |
T6,T7,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T15,T18,T20 |
0 |
Covered |
T6,T7,T1 |
Assert Coverage for Instance : tb.dut.u_io_step_down_req_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471662723 |
467798637 |
0 |
0 |
T1 |
192700 |
192524 |
0 |
0 |
T2 |
239754 |
239619 |
0 |
0 |
T4 |
30982 |
3859 |
0 |
0 |
T5 |
81550 |
5620 |
0 |
0 |
T6 |
4846 |
4697 |
0 |
0 |
T7 |
4182 |
4061 |
0 |
0 |
T15 |
4708 |
4573 |
0 |
0 |
T16 |
1304 |
1074 |
0 |
0 |
T17 |
116680 |
15680 |
0 |
0 |
T18 |
2243 |
2094 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471662723 |
467792145 |
0 |
2415 |
T1 |
192700 |
192521 |
0 |
3 |
T2 |
239754 |
239616 |
0 |
3 |
T4 |
30982 |
3841 |
0 |
3 |
T5 |
81550 |
5578 |
0 |
3 |
T6 |
4846 |
4694 |
0 |
3 |
T7 |
4182 |
4058 |
0 |
3 |
T15 |
4708 |
4570 |
0 |
3 |
T16 |
1304 |
1071 |
0 |
3 |
T17 |
116680 |
15623 |
0 |
3 |
T18 |
2243 |
2091 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471662723 |
28418 |
0 |
0 |
T2 |
239754 |
0 |
0 |
0 |
T4 |
30982 |
0 |
0 |
0 |
T5 |
81550 |
0 |
0 |
0 |
T15 |
4708 |
21 |
0 |
0 |
T16 |
1304 |
0 |
0 |
0 |
T17 |
116680 |
0 |
0 |
0 |
T18 |
2243 |
53 |
0 |
0 |
T19 |
1777 |
0 |
0 |
0 |
T20 |
9079 |
58 |
0 |
0 |
T24 |
1925 |
0 |
0 |
0 |
T40 |
0 |
44 |
0 |
0 |
T41 |
0 |
17 |
0 |
0 |
T74 |
0 |
50 |
0 |
0 |
T86 |
0 |
23 |
0 |
0 |
T127 |
0 |
13 |
0 |
0 |
T128 |
0 |
26 |
0 |
0 |
T129 |
0 |
37 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153051899 |
150884266 |
0 |
0 |
T1 |
126464 |
126349 |
0 |
0 |
T2 |
44954 |
44929 |
0 |
0 |
T4 |
27755 |
3461 |
0 |
0 |
T5 |
42475 |
2939 |
0 |
0 |
T6 |
1210 |
1174 |
0 |
0 |
T7 |
1088 |
1057 |
0 |
0 |
T15 |
1225 |
1191 |
0 |
0 |
T16 |
1445 |
1212 |
0 |
0 |
T17 |
24308 |
3284 |
0 |
0 |
T18 |
2336 |
2181 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153051899 |
150884266 |
0 |
0 |
T1 |
126464 |
126349 |
0 |
0 |
T2 |
44954 |
44929 |
0 |
0 |
T4 |
27755 |
3461 |
0 |
0 |
T5 |
42475 |
2939 |
0 |
0 |
T6 |
1210 |
1174 |
0 |
0 |
T7 |
1088 |
1057 |
0 |
0 |
T15 |
1225 |
1191 |
0 |
0 |
T16 |
1445 |
1212 |
0 |
0 |
T17 |
24308 |
3284 |
0 |
0 |
T18 |
2336 |
2181 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153051899 |
150884266 |
0 |
0 |
T1 |
126464 |
126349 |
0 |
0 |
T2 |
44954 |
44929 |
0 |
0 |
T4 |
27755 |
3461 |
0 |
0 |
T5 |
42475 |
2939 |
0 |
0 |
T6 |
1210 |
1174 |
0 |
0 |
T7 |
1088 |
1057 |
0 |
0 |
T15 |
1225 |
1191 |
0 |
0 |
T16 |
1445 |
1212 |
0 |
0 |
T17 |
24308 |
3284 |
0 |
0 |
T18 |
2336 |
2181 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153051899 |
150884266 |
0 |
0 |
T1 |
126464 |
126349 |
0 |
0 |
T2 |
44954 |
44929 |
0 |
0 |
T4 |
27755 |
3461 |
0 |
0 |
T5 |
42475 |
2939 |
0 |
0 |
T6 |
1210 |
1174 |
0 |
0 |
T7 |
1088 |
1057 |
0 |
0 |
T15 |
1225 |
1191 |
0 |
0 |
T16 |
1445 |
1212 |
0 |
0 |
T17 |
24308 |
3284 |
0 |
0 |
T18 |
2336 |
2181 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T1 |
1 | Covered | T15,T18,T20 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T1 |
1 | Covered | T15,T18,T20 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T1 |
1 | Covered | T15,T18,T20 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T1 |
1 | Covered | T15,T18,T20 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T15,T18,T20 |
0 |
Covered |
T6,T7,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T15,T18,T20 |
0 |
Covered |
T6,T7,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T15,T18,T20 |
0 |
Covered |
T6,T7,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T15,T18,T20 |
0 |
Covered |
T6,T7,T1 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153051899 |
150884266 |
0 |
0 |
T1 |
126464 |
126349 |
0 |
0 |
T2 |
44954 |
44929 |
0 |
0 |
T4 |
27755 |
3461 |
0 |
0 |
T5 |
42475 |
2939 |
0 |
0 |
T6 |
1210 |
1174 |
0 |
0 |
T7 |
1088 |
1057 |
0 |
0 |
T15 |
1225 |
1191 |
0 |
0 |
T16 |
1445 |
1212 |
0 |
0 |
T17 |
24308 |
3284 |
0 |
0 |
T18 |
2336 |
2181 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153051899 |
150877622 |
0 |
2415 |
T1 |
126464 |
126346 |
0 |
3 |
T2 |
44954 |
44926 |
0 |
3 |
T4 |
27755 |
3443 |
0 |
3 |
T5 |
42475 |
2884 |
0 |
3 |
T6 |
1210 |
1171 |
0 |
3 |
T7 |
1088 |
1054 |
0 |
3 |
T15 |
1225 |
1188 |
0 |
3 |
T16 |
1445 |
1209 |
0 |
3 |
T17 |
24308 |
3209 |
0 |
3 |
T18 |
2336 |
2178 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153051899 |
17623 |
0 |
0 |
T2 |
44954 |
0 |
0 |
0 |
T4 |
27755 |
0 |
0 |
0 |
T5 |
42475 |
0 |
0 |
0 |
T15 |
1225 |
11 |
0 |
0 |
T16 |
1445 |
0 |
0 |
0 |
T17 |
24308 |
0 |
0 |
0 |
T18 |
2336 |
77 |
0 |
0 |
T19 |
1777 |
0 |
0 |
0 |
T20 |
2269 |
46 |
0 |
0 |
T24 |
1310 |
0 |
0 |
0 |
T40 |
0 |
5 |
0 |
0 |
T41 |
0 |
21 |
0 |
0 |
T74 |
0 |
7 |
0 |
0 |
T86 |
0 |
29 |
0 |
0 |
T127 |
0 |
11 |
0 |
0 |
T128 |
0 |
34 |
0 |
0 |
T129 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T1 |
1 | Covered | T15,T18,T20 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T1 |
1 | Covered | T15,T18,T20 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T1 |
1 | Covered | T15,T18,T20 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T1 |
1 | Covered | T15,T18,T20 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T15,T18,T20 |
0 |
Covered |
T6,T7,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T15,T18,T20 |
0 |
Covered |
T6,T7,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T15,T18,T20 |
0 |
Covered |
T6,T7,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T15,T18,T20 |
0 |
Covered |
T6,T7,T1 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153051899 |
150884266 |
0 |
0 |
T1 |
126464 |
126349 |
0 |
0 |
T2 |
44954 |
44929 |
0 |
0 |
T4 |
27755 |
3461 |
0 |
0 |
T5 |
42475 |
2939 |
0 |
0 |
T6 |
1210 |
1174 |
0 |
0 |
T7 |
1088 |
1057 |
0 |
0 |
T15 |
1225 |
1191 |
0 |
0 |
T16 |
1445 |
1212 |
0 |
0 |
T17 |
24308 |
3284 |
0 |
0 |
T18 |
2336 |
2181 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153051899 |
150877622 |
0 |
2415 |
T1 |
126464 |
126346 |
0 |
3 |
T2 |
44954 |
44926 |
0 |
3 |
T4 |
27755 |
3443 |
0 |
3 |
T5 |
42475 |
2884 |
0 |
3 |
T6 |
1210 |
1171 |
0 |
3 |
T7 |
1088 |
1054 |
0 |
3 |
T15 |
1225 |
1188 |
0 |
3 |
T16 |
1445 |
1209 |
0 |
3 |
T17 |
24308 |
3209 |
0 |
3 |
T18 |
2336 |
2178 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153051899 |
19930 |
0 |
0 |
T2 |
44954 |
0 |
0 |
0 |
T4 |
27755 |
0 |
0 |
0 |
T5 |
42475 |
0 |
0 |
0 |
T15 |
1225 |
18 |
0 |
0 |
T16 |
1445 |
0 |
0 |
0 |
T17 |
24308 |
0 |
0 |
0 |
T18 |
2336 |
51 |
0 |
0 |
T19 |
1777 |
0 |
0 |
0 |
T20 |
2269 |
29 |
0 |
0 |
T24 |
1310 |
0 |
0 |
0 |
T40 |
0 |
39 |
0 |
0 |
T41 |
0 |
15 |
0 |
0 |
T74 |
0 |
50 |
0 |
0 |
T86 |
0 |
29 |
0 |
0 |
T127 |
0 |
11 |
0 |
0 |
T128 |
0 |
33 |
0 |
0 |
T129 |
0 |
38 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
502534067 |
500463008 |
0 |
0 |
T1 |
200736 |
200681 |
0 |
0 |
T2 |
249751 |
249653 |
0 |
0 |
T4 |
32274 |
20662 |
0 |
0 |
T5 |
84950 |
41396 |
0 |
0 |
T6 |
5047 |
4993 |
0 |
0 |
T7 |
4358 |
4260 |
0 |
0 |
T15 |
4905 |
4836 |
0 |
0 |
T16 |
1371 |
1245 |
0 |
0 |
T17 |
121545 |
68447 |
0 |
0 |
T18 |
2336 |
2224 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
502534067 |
500463008 |
0 |
0 |
T1 |
200736 |
200681 |
0 |
0 |
T2 |
249751 |
249653 |
0 |
0 |
T4 |
32274 |
20662 |
0 |
0 |
T5 |
84950 |
41396 |
0 |
0 |
T6 |
5047 |
4993 |
0 |
0 |
T7 |
4358 |
4260 |
0 |
0 |
T15 |
4905 |
4836 |
0 |
0 |
T16 |
1371 |
1245 |
0 |
0 |
T17 |
121545 |
68447 |
0 |
0 |
T18 |
2336 |
2224 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471662723 |
469714363 |
0 |
0 |
T1 |
192700 |
192648 |
0 |
0 |
T2 |
239754 |
239660 |
0 |
0 |
T4 |
30982 |
19835 |
0 |
0 |
T5 |
81550 |
39738 |
0 |
0 |
T6 |
4846 |
4793 |
0 |
0 |
T7 |
4182 |
4089 |
0 |
0 |
T15 |
4708 |
4642 |
0 |
0 |
T16 |
1304 |
1183 |
0 |
0 |
T17 |
116680 |
65708 |
0 |
0 |
T18 |
2243 |
2135 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471662723 |
469714363 |
0 |
0 |
T1 |
192700 |
192648 |
0 |
0 |
T2 |
239754 |
239660 |
0 |
0 |
T4 |
30982 |
19835 |
0 |
0 |
T5 |
81550 |
39738 |
0 |
0 |
T6 |
4846 |
4793 |
0 |
0 |
T7 |
4182 |
4089 |
0 |
0 |
T15 |
4708 |
4642 |
0 |
0 |
T16 |
1304 |
1183 |
0 |
0 |
T17 |
116680 |
65708 |
0 |
0 |
T18 |
2243 |
2135 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
236949594 |
236949594 |
0 |
0 |
T1 |
96324 |
96324 |
0 |
0 |
T2 |
119830 |
119830 |
0 |
0 |
T4 |
9919 |
9919 |
0 |
0 |
T5 |
19873 |
19873 |
0 |
0 |
T6 |
2397 |
2397 |
0 |
0 |
T7 |
2045 |
2045 |
0 |
0 |
T15 |
2434 |
2434 |
0 |
0 |
T16 |
592 |
592 |
0 |
0 |
T17 |
32859 |
32859 |
0 |
0 |
T18 |
1285 |
1285 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
236949594 |
236949594 |
0 |
0 |
T1 |
96324 |
96324 |
0 |
0 |
T2 |
119830 |
119830 |
0 |
0 |
T4 |
9919 |
9919 |
0 |
0 |
T5 |
19873 |
19873 |
0 |
0 |
T6 |
2397 |
2397 |
0 |
0 |
T7 |
2045 |
2045 |
0 |
0 |
T15 |
2434 |
2434 |
0 |
0 |
T16 |
592 |
592 |
0 |
0 |
T17 |
32859 |
32859 |
0 |
0 |
T18 |
1285 |
1285 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118474156 |
118474156 |
0 |
0 |
T1 |
48162 |
48162 |
0 |
0 |
T2 |
59915 |
59915 |
0 |
0 |
T4 |
4960 |
4960 |
0 |
0 |
T5 |
9936 |
9936 |
0 |
0 |
T6 |
1198 |
1198 |
0 |
0 |
T7 |
1022 |
1022 |
0 |
0 |
T15 |
1217 |
1217 |
0 |
0 |
T16 |
296 |
296 |
0 |
0 |
T17 |
16431 |
16431 |
0 |
0 |
T18 |
640 |
640 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118474156 |
118474156 |
0 |
0 |
T1 |
48162 |
48162 |
0 |
0 |
T2 |
59915 |
59915 |
0 |
0 |
T4 |
4960 |
4960 |
0 |
0 |
T5 |
9936 |
9936 |
0 |
0 |
T6 |
1198 |
1198 |
0 |
0 |
T7 |
1022 |
1022 |
0 |
0 |
T15 |
1217 |
1217 |
0 |
0 |
T16 |
296 |
296 |
0 |
0 |
T17 |
16431 |
16431 |
0 |
0 |
T18 |
640 |
640 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
241191408 |
240200461 |
0 |
0 |
T1 |
96355 |
96329 |
0 |
0 |
T2 |
119882 |
119836 |
0 |
0 |
T4 |
15492 |
9918 |
0 |
0 |
T5 |
40776 |
19869 |
0 |
0 |
T6 |
2422 |
2397 |
0 |
0 |
T7 |
2091 |
2044 |
0 |
0 |
T15 |
2354 |
2321 |
0 |
0 |
T16 |
673 |
612 |
0 |
0 |
T17 |
58342 |
32856 |
0 |
0 |
T18 |
1121 |
1068 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
241191408 |
240200461 |
0 |
0 |
T1 |
96355 |
96329 |
0 |
0 |
T2 |
119882 |
119836 |
0 |
0 |
T4 |
15492 |
9918 |
0 |
0 |
T5 |
40776 |
19869 |
0 |
0 |
T6 |
2422 |
2397 |
0 |
0 |
T7 |
2091 |
2044 |
0 |
0 |
T15 |
2354 |
2321 |
0 |
0 |
T16 |
673 |
612 |
0 |
0 |
T17 |
58342 |
32856 |
0 |
0 |
T18 |
1121 |
1068 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Assert Coverage for Instance : tb.dut.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153051899 |
150884266 |
0 |
0 |
T1 |
126464 |
126349 |
0 |
0 |
T2 |
44954 |
44929 |
0 |
0 |
T4 |
27755 |
3461 |
0 |
0 |
T5 |
42475 |
2939 |
0 |
0 |
T6 |
1210 |
1174 |
0 |
0 |
T7 |
1088 |
1057 |
0 |
0 |
T15 |
1225 |
1191 |
0 |
0 |
T16 |
1445 |
1212 |
0 |
0 |
T17 |
24308 |
3284 |
0 |
0 |
T18 |
2336 |
2181 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153051899 |
150877622 |
0 |
2415 |
T1 |
126464 |
126346 |
0 |
3 |
T2 |
44954 |
44926 |
0 |
3 |
T4 |
27755 |
3443 |
0 |
3 |
T5 |
42475 |
2884 |
0 |
3 |
T6 |
1210 |
1171 |
0 |
3 |
T7 |
1088 |
1054 |
0 |
3 |
T15 |
1225 |
1188 |
0 |
3 |
T16 |
1445 |
1209 |
0 |
3 |
T17 |
24308 |
3209 |
0 |
3 |
T18 |
2336 |
2178 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153051899 |
150884266 |
0 |
0 |
T1 |
126464 |
126349 |
0 |
0 |
T2 |
44954 |
44929 |
0 |
0 |
T4 |
27755 |
3461 |
0 |
0 |
T5 |
42475 |
2939 |
0 |
0 |
T6 |
1210 |
1174 |
0 |
0 |
T7 |
1088 |
1057 |
0 |
0 |
T15 |
1225 |
1191 |
0 |
0 |
T16 |
1445 |
1212 |
0 |
0 |
T17 |
24308 |
3284 |
0 |
0 |
T18 |
2336 |
2181 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153051899 |
150877622 |
0 |
2415 |
T1 |
126464 |
126346 |
0 |
3 |
T2 |
44954 |
44926 |
0 |
3 |
T4 |
27755 |
3443 |
0 |
3 |
T5 |
42475 |
2884 |
0 |
3 |
T6 |
1210 |
1171 |
0 |
3 |
T7 |
1088 |
1054 |
0 |
3 |
T15 |
1225 |
1188 |
0 |
3 |
T16 |
1445 |
1209 |
0 |
3 |
T17 |
24308 |
3209 |
0 |
3 |
T18 |
2336 |
2178 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153051899 |
150884266 |
0 |
0 |
T1 |
126464 |
126349 |
0 |
0 |
T2 |
44954 |
44929 |
0 |
0 |
T4 |
27755 |
3461 |
0 |
0 |
T5 |
42475 |
2939 |
0 |
0 |
T6 |
1210 |
1174 |
0 |
0 |
T7 |
1088 |
1057 |
0 |
0 |
T15 |
1225 |
1191 |
0 |
0 |
T16 |
1445 |
1212 |
0 |
0 |
T17 |
24308 |
3284 |
0 |
0 |
T18 |
2336 |
2181 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153051899 |
150877622 |
0 |
2415 |
T1 |
126464 |
126346 |
0 |
3 |
T2 |
44954 |
44926 |
0 |
3 |
T4 |
27755 |
3443 |
0 |
3 |
T5 |
42475 |
2884 |
0 |
3 |
T6 |
1210 |
1171 |
0 |
3 |
T7 |
1088 |
1054 |
0 |
3 |
T15 |
1225 |
1188 |
0 |
3 |
T16 |
1445 |
1209 |
0 |
3 |
T17 |
24308 |
3209 |
0 |
3 |
T18 |
2336 |
2178 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153051899 |
150884266 |
0 |
0 |
T1 |
126464 |
126349 |
0 |
0 |
T2 |
44954 |
44929 |
0 |
0 |
T4 |
27755 |
3461 |
0 |
0 |
T5 |
42475 |
2939 |
0 |
0 |
T6 |
1210 |
1174 |
0 |
0 |
T7 |
1088 |
1057 |
0 |
0 |
T15 |
1225 |
1191 |
0 |
0 |
T16 |
1445 |
1212 |
0 |
0 |
T17 |
24308 |
3284 |
0 |
0 |
T18 |
2336 |
2181 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153051899 |
150877622 |
0 |
2415 |
T1 |
126464 |
126346 |
0 |
3 |
T2 |
44954 |
44926 |
0 |
3 |
T4 |
27755 |
3443 |
0 |
3 |
T5 |
42475 |
2884 |
0 |
3 |
T6 |
1210 |
1171 |
0 |
3 |
T7 |
1088 |
1054 |
0 |
3 |
T15 |
1225 |
1188 |
0 |
3 |
T16 |
1445 |
1209 |
0 |
3 |
T17 |
24308 |
3209 |
0 |
3 |
T18 |
2336 |
2178 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153051899 |
150884266 |
0 |
0 |
T1 |
126464 |
126349 |
0 |
0 |
T2 |
44954 |
44929 |
0 |
0 |
T4 |
27755 |
3461 |
0 |
0 |
T5 |
42475 |
2939 |
0 |
0 |
T6 |
1210 |
1174 |
0 |
0 |
T7 |
1088 |
1057 |
0 |
0 |
T15 |
1225 |
1191 |
0 |
0 |
T16 |
1445 |
1212 |
0 |
0 |
T17 |
24308 |
3284 |
0 |
0 |
T18 |
2336 |
2181 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153051899 |
150877622 |
0 |
2415 |
T1 |
126464 |
126346 |
0 |
3 |
T2 |
44954 |
44926 |
0 |
3 |
T4 |
27755 |
3443 |
0 |
3 |
T5 |
42475 |
2884 |
0 |
3 |
T6 |
1210 |
1171 |
0 |
3 |
T7 |
1088 |
1054 |
0 |
3 |
T15 |
1225 |
1188 |
0 |
3 |
T16 |
1445 |
1209 |
0 |
3 |
T17 |
24308 |
3209 |
0 |
3 |
T18 |
2336 |
2178 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153051899 |
150884266 |
0 |
0 |
T1 |
126464 |
126349 |
0 |
0 |
T2 |
44954 |
44929 |
0 |
0 |
T4 |
27755 |
3461 |
0 |
0 |
T5 |
42475 |
2939 |
0 |
0 |
T6 |
1210 |
1174 |
0 |
0 |
T7 |
1088 |
1057 |
0 |
0 |
T15 |
1225 |
1191 |
0 |
0 |
T16 |
1445 |
1212 |
0 |
0 |
T17 |
24308 |
3284 |
0 |
0 |
T18 |
2336 |
2181 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153051899 |
150877622 |
0 |
2415 |
T1 |
126464 |
126346 |
0 |
3 |
T2 |
44954 |
44926 |
0 |
3 |
T4 |
27755 |
3443 |
0 |
3 |
T5 |
42475 |
2884 |
0 |
3 |
T6 |
1210 |
1171 |
0 |
3 |
T7 |
1088 |
1054 |
0 |
3 |
T15 |
1225 |
1188 |
0 |
3 |
T16 |
1445 |
1209 |
0 |
3 |
T17 |
24308 |
3209 |
0 |
3 |
T18 |
2336 |
2178 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153051899 |
150884266 |
0 |
0 |
T1 |
126464 |
126349 |
0 |
0 |
T2 |
44954 |
44929 |
0 |
0 |
T4 |
27755 |
3461 |
0 |
0 |
T5 |
42475 |
2939 |
0 |
0 |
T6 |
1210 |
1174 |
0 |
0 |
T7 |
1088 |
1057 |
0 |
0 |
T15 |
1225 |
1191 |
0 |
0 |
T16 |
1445 |
1212 |
0 |
0 |
T17 |
24308 |
3284 |
0 |
0 |
T18 |
2336 |
2181 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153051899 |
150884266 |
0 |
0 |
T1 |
126464 |
126349 |
0 |
0 |
T2 |
44954 |
44929 |
0 |
0 |
T4 |
27755 |
3461 |
0 |
0 |
T5 |
42475 |
2939 |
0 |
0 |
T6 |
1210 |
1174 |
0 |
0 |
T7 |
1088 |
1057 |
0 |
0 |
T15 |
1225 |
1191 |
0 |
0 |
T16 |
1445 |
1212 |
0 |
0 |
T17 |
24308 |
3284 |
0 |
0 |
T18 |
2336 |
2181 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153051899 |
150884266 |
0 |
0 |
T1 |
126464 |
126349 |
0 |
0 |
T2 |
44954 |
44929 |
0 |
0 |
T4 |
27755 |
3461 |
0 |
0 |
T5 |
42475 |
2939 |
0 |
0 |
T6 |
1210 |
1174 |
0 |
0 |
T7 |
1088 |
1057 |
0 |
0 |
T15 |
1225 |
1191 |
0 |
0 |
T16 |
1445 |
1212 |
0 |
0 |
T17 |
24308 |
3284 |
0 |
0 |
T18 |
2336 |
2181 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153051899 |
150884266 |
0 |
0 |
T1 |
126464 |
126349 |
0 |
0 |
T2 |
44954 |
44929 |
0 |
0 |
T4 |
27755 |
3461 |
0 |
0 |
T5 |
42475 |
2939 |
0 |
0 |
T6 |
1210 |
1174 |
0 |
0 |
T7 |
1088 |
1057 |
0 |
0 |
T15 |
1225 |
1191 |
0 |
0 |
T16 |
1445 |
1212 |
0 |
0 |
T17 |
24308 |
3284 |
0 |
0 |
T18 |
2336 |
2181 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153051899 |
150884266 |
0 |
0 |
T1 |
126464 |
126349 |
0 |
0 |
T2 |
44954 |
44929 |
0 |
0 |
T4 |
27755 |
3461 |
0 |
0 |
T5 |
42475 |
2939 |
0 |
0 |
T6 |
1210 |
1174 |
0 |
0 |
T7 |
1088 |
1057 |
0 |
0 |
T15 |
1225 |
1191 |
0 |
0 |
T16 |
1445 |
1212 |
0 |
0 |
T17 |
24308 |
3284 |
0 |
0 |
T18 |
2336 |
2181 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153051899 |
150884266 |
0 |
0 |
T1 |
126464 |
126349 |
0 |
0 |
T2 |
44954 |
44929 |
0 |
0 |
T4 |
27755 |
3461 |
0 |
0 |
T5 |
42475 |
2939 |
0 |
0 |
T6 |
1210 |
1174 |
0 |
0 |
T7 |
1088 |
1057 |
0 |
0 |
T15 |
1225 |
1191 |
0 |
0 |
T16 |
1445 |
1212 |
0 |
0 |
T17 |
24308 |
3284 |
0 |
0 |
T18 |
2336 |
2181 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153051899 |
150884266 |
0 |
0 |
T1 |
126464 |
126349 |
0 |
0 |
T2 |
44954 |
44929 |
0 |
0 |
T4 |
27755 |
3461 |
0 |
0 |
T5 |
42475 |
2939 |
0 |
0 |
T6 |
1210 |
1174 |
0 |
0 |
T7 |
1088 |
1057 |
0 |
0 |
T15 |
1225 |
1191 |
0 |
0 |
T16 |
1445 |
1212 |
0 |
0 |
T17 |
24308 |
3284 |
0 |
0 |
T18 |
2336 |
2181 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153051899 |
150884266 |
0 |
0 |
T1 |
126464 |
126349 |
0 |
0 |
T2 |
44954 |
44929 |
0 |
0 |
T4 |
27755 |
3461 |
0 |
0 |
T5 |
42475 |
2939 |
0 |
0 |
T6 |
1210 |
1174 |
0 |
0 |
T7 |
1088 |
1057 |
0 |
0 |
T15 |
1225 |
1191 |
0 |
0 |
T16 |
1445 |
1212 |
0 |
0 |
T17 |
24308 |
3284 |
0 |
0 |
T18 |
2336 |
2181 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T1 |
1 | Covered | T6,T7,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T1 |
1 | Covered | T6,T7,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T1 |
1 | Covered | T6,T7,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T1 |
1 | Covered | T6,T7,T1 |
Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T1 |
0 |
Covered |
T6,T7,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T1 |
0 |
Covered |
T6,T7,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T1 |
0 |
Covered |
T6,T7,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T1 |
0 |
Covered |
T6,T7,T1 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
502534067 |
498440019 |
0 |
0 |
T1 |
200736 |
200552 |
0 |
0 |
T2 |
249751 |
249611 |
0 |
0 |
T4 |
32274 |
4020 |
0 |
0 |
T5 |
84950 |
5853 |
0 |
0 |
T6 |
5047 |
4893 |
0 |
0 |
T7 |
4358 |
4231 |
0 |
0 |
T15 |
4905 |
4764 |
0 |
0 |
T16 |
1371 |
1130 |
0 |
0 |
T17 |
121545 |
16333 |
0 |
0 |
T18 |
2336 |
2181 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
502534067 |
498433493 |
0 |
2415 |
T1 |
200736 |
200549 |
0 |
3 |
T2 |
249751 |
249608 |
0 |
3 |
T4 |
32274 |
4002 |
0 |
3 |
T5 |
84950 |
5811 |
0 |
3 |
T6 |
5047 |
4890 |
0 |
3 |
T7 |
4358 |
4228 |
0 |
3 |
T15 |
4905 |
4761 |
0 |
3 |
T16 |
1371 |
1127 |
0 |
3 |
T17 |
121545 |
16276 |
0 |
3 |
T18 |
2336 |
2178 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
502534067 |
34548 |
0 |
0 |
T1 |
200736 |
1 |
0 |
0 |
T2 |
249751 |
1 |
0 |
0 |
T4 |
32274 |
6 |
0 |
0 |
T5 |
84950 |
14 |
0 |
0 |
T6 |
5047 |
4 |
0 |
0 |
T7 |
4358 |
11 |
0 |
0 |
T15 |
4905 |
3 |
0 |
0 |
T16 |
1371 |
8 |
0 |
0 |
T17 |
121545 |
19 |
0 |
0 |
T18 |
2336 |
21 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
502534067 |
498440019 |
0 |
0 |
T1 |
200736 |
200552 |
0 |
0 |
T2 |
249751 |
249611 |
0 |
0 |
T4 |
32274 |
4020 |
0 |
0 |
T5 |
84950 |
5853 |
0 |
0 |
T6 |
5047 |
4893 |
0 |
0 |
T7 |
4358 |
4231 |
0 |
0 |
T15 |
4905 |
4764 |
0 |
0 |
T16 |
1371 |
1130 |
0 |
0 |
T17 |
121545 |
16333 |
0 |
0 |
T18 |
2336 |
2181 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
502534067 |
498440019 |
0 |
0 |
T1 |
200736 |
200552 |
0 |
0 |
T2 |
249751 |
249611 |
0 |
0 |
T4 |
32274 |
4020 |
0 |
0 |
T5 |
84950 |
5853 |
0 |
0 |
T6 |
5047 |
4893 |
0 |
0 |
T7 |
4358 |
4231 |
0 |
0 |
T15 |
4905 |
4764 |
0 |
0 |
T16 |
1371 |
1130 |
0 |
0 |
T17 |
121545 |
16333 |
0 |
0 |
T18 |
2336 |
2181 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T1 |
1 | Covered | T6,T7,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T1 |
1 | Covered | T6,T7,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T1 |
1 | Covered | T6,T7,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T1 |
1 | Covered | T6,T7,T1 |
Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T1 |
0 |
Covered |
T6,T7,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T1 |
0 |
Covered |
T6,T7,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T1 |
0 |
Covered |
T6,T7,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T1 |
0 |
Covered |
T6,T7,T1 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
502534067 |
498440019 |
0 |
0 |
T1 |
200736 |
200552 |
0 |
0 |
T2 |
249751 |
249611 |
0 |
0 |
T4 |
32274 |
4020 |
0 |
0 |
T5 |
84950 |
5853 |
0 |
0 |
T6 |
5047 |
4893 |
0 |
0 |
T7 |
4358 |
4231 |
0 |
0 |
T15 |
4905 |
4764 |
0 |
0 |
T16 |
1371 |
1130 |
0 |
0 |
T17 |
121545 |
16333 |
0 |
0 |
T18 |
2336 |
2181 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
502534067 |
498433493 |
0 |
2415 |
T1 |
200736 |
200549 |
0 |
3 |
T2 |
249751 |
249608 |
0 |
3 |
T4 |
32274 |
4002 |
0 |
3 |
T5 |
84950 |
5811 |
0 |
3 |
T6 |
5047 |
4890 |
0 |
3 |
T7 |
4358 |
4228 |
0 |
3 |
T15 |
4905 |
4761 |
0 |
3 |
T16 |
1371 |
1127 |
0 |
3 |
T17 |
121545 |
16276 |
0 |
3 |
T18 |
2336 |
2178 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
502534067 |
34518 |
0 |
0 |
T1 |
200736 |
1 |
0 |
0 |
T2 |
249751 |
1 |
0 |
0 |
T4 |
32274 |
6 |
0 |
0 |
T5 |
84950 |
14 |
0 |
0 |
T6 |
5047 |
4 |
0 |
0 |
T7 |
4358 |
17 |
0 |
0 |
T15 |
4905 |
7 |
0 |
0 |
T16 |
1371 |
8 |
0 |
0 |
T17 |
121545 |
19 |
0 |
0 |
T18 |
2336 |
19 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
502534067 |
498440019 |
0 |
0 |
T1 |
200736 |
200552 |
0 |
0 |
T2 |
249751 |
249611 |
0 |
0 |
T4 |
32274 |
4020 |
0 |
0 |
T5 |
84950 |
5853 |
0 |
0 |
T6 |
5047 |
4893 |
0 |
0 |
T7 |
4358 |
4231 |
0 |
0 |
T15 |
4905 |
4764 |
0 |
0 |
T16 |
1371 |
1130 |
0 |
0 |
T17 |
121545 |
16333 |
0 |
0 |
T18 |
2336 |
2181 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
502534067 |
498440019 |
0 |
0 |
T1 |
200736 |
200552 |
0 |
0 |
T2 |
249751 |
249611 |
0 |
0 |
T4 |
32274 |
4020 |
0 |
0 |
T5 |
84950 |
5853 |
0 |
0 |
T6 |
5047 |
4893 |
0 |
0 |
T7 |
4358 |
4231 |
0 |
0 |
T15 |
4905 |
4764 |
0 |
0 |
T16 |
1371 |
1130 |
0 |
0 |
T17 |
121545 |
16333 |
0 |
0 |
T18 |
2336 |
2181 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T1 |
1 | Covered | T6,T7,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T1 |
1 | Covered | T6,T7,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T1 |
1 | Covered | T6,T7,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T1 |
1 | Covered | T6,T7,T1 |
Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T1 |
0 |
Covered |
T6,T7,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T1 |
0 |
Covered |
T6,T7,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T1 |
0 |
Covered |
T6,T7,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T1 |
0 |
Covered |
T6,T7,T1 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
502534067 |
498440019 |
0 |
0 |
T1 |
200736 |
200552 |
0 |
0 |
T2 |
249751 |
249611 |
0 |
0 |
T4 |
32274 |
4020 |
0 |
0 |
T5 |
84950 |
5853 |
0 |
0 |
T6 |
5047 |
4893 |
0 |
0 |
T7 |
4358 |
4231 |
0 |
0 |
T15 |
4905 |
4764 |
0 |
0 |
T16 |
1371 |
1130 |
0 |
0 |
T17 |
121545 |
16333 |
0 |
0 |
T18 |
2336 |
2181 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
502534067 |
498433493 |
0 |
2415 |
T1 |
200736 |
200549 |
0 |
3 |
T2 |
249751 |
249608 |
0 |
3 |
T4 |
32274 |
4002 |
0 |
3 |
T5 |
84950 |
5811 |
0 |
3 |
T6 |
5047 |
4890 |
0 |
3 |
T7 |
4358 |
4228 |
0 |
3 |
T15 |
4905 |
4761 |
0 |
3 |
T16 |
1371 |
1127 |
0 |
3 |
T17 |
121545 |
16276 |
0 |
3 |
T18 |
2336 |
2178 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
502534067 |
35024 |
0 |
0 |
T1 |
200736 |
1 |
0 |
0 |
T2 |
249751 |
1 |
0 |
0 |
T4 |
32274 |
6 |
0 |
0 |
T5 |
84950 |
14 |
0 |
0 |
T6 |
5047 |
4 |
0 |
0 |
T7 |
4358 |
19 |
0 |
0 |
T15 |
4905 |
7 |
0 |
0 |
T16 |
1371 |
11 |
0 |
0 |
T17 |
121545 |
19 |
0 |
0 |
T18 |
2336 |
22 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
502534067 |
498440019 |
0 |
0 |
T1 |
200736 |
200552 |
0 |
0 |
T2 |
249751 |
249611 |
0 |
0 |
T4 |
32274 |
4020 |
0 |
0 |
T5 |
84950 |
5853 |
0 |
0 |
T6 |
5047 |
4893 |
0 |
0 |
T7 |
4358 |
4231 |
0 |
0 |
T15 |
4905 |
4764 |
0 |
0 |
T16 |
1371 |
1130 |
0 |
0 |
T17 |
121545 |
16333 |
0 |
0 |
T18 |
2336 |
2181 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
502534067 |
498440019 |
0 |
0 |
T1 |
200736 |
200552 |
0 |
0 |
T2 |
249751 |
249611 |
0 |
0 |
T4 |
32274 |
4020 |
0 |
0 |
T5 |
84950 |
5853 |
0 |
0 |
T6 |
5047 |
4893 |
0 |
0 |
T7 |
4358 |
4231 |
0 |
0 |
T15 |
4905 |
4764 |
0 |
0 |
T16 |
1371 |
1130 |
0 |
0 |
T17 |
121545 |
16333 |
0 |
0 |
T18 |
2336 |
2181 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T1 |
1 | Covered | T6,T7,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T1 |
1 | Covered | T6,T7,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T1 |
1 | Covered | T6,T7,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T1 |
1 | Covered | T6,T7,T1 |
Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T1 |
0 |
Covered |
T6,T7,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T1 |
0 |
Covered |
T6,T7,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T1 |
0 |
Covered |
T6,T7,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T1 |
0 |
Covered |
T6,T7,T1 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
502534067 |
498440019 |
0 |
0 |
T1 |
200736 |
200552 |
0 |
0 |
T2 |
249751 |
249611 |
0 |
0 |
T4 |
32274 |
4020 |
0 |
0 |
T5 |
84950 |
5853 |
0 |
0 |
T6 |
5047 |
4893 |
0 |
0 |
T7 |
4358 |
4231 |
0 |
0 |
T15 |
4905 |
4764 |
0 |
0 |
T16 |
1371 |
1130 |
0 |
0 |
T17 |
121545 |
16333 |
0 |
0 |
T18 |
2336 |
2181 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
502534067 |
498433493 |
0 |
2415 |
T1 |
200736 |
200549 |
0 |
3 |
T2 |
249751 |
249608 |
0 |
3 |
T4 |
32274 |
4002 |
0 |
3 |
T5 |
84950 |
5811 |
0 |
3 |
T6 |
5047 |
4890 |
0 |
3 |
T7 |
4358 |
4228 |
0 |
3 |
T15 |
4905 |
4761 |
0 |
3 |
T16 |
1371 |
1127 |
0 |
3 |
T17 |
121545 |
16276 |
0 |
3 |
T18 |
2336 |
2178 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
502534067 |
34872 |
0 |
0 |
T1 |
200736 |
1 |
0 |
0 |
T2 |
249751 |
1 |
0 |
0 |
T4 |
32274 |
6 |
0 |
0 |
T5 |
84950 |
14 |
0 |
0 |
T6 |
5047 |
4 |
0 |
0 |
T7 |
4358 |
15 |
0 |
0 |
T15 |
4905 |
8 |
0 |
0 |
T16 |
1371 |
7 |
0 |
0 |
T17 |
121545 |
19 |
0 |
0 |
T18 |
2336 |
19 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
502534067 |
498440019 |
0 |
0 |
T1 |
200736 |
200552 |
0 |
0 |
T2 |
249751 |
249611 |
0 |
0 |
T4 |
32274 |
4020 |
0 |
0 |
T5 |
84950 |
5853 |
0 |
0 |
T6 |
5047 |
4893 |
0 |
0 |
T7 |
4358 |
4231 |
0 |
0 |
T15 |
4905 |
4764 |
0 |
0 |
T16 |
1371 |
1130 |
0 |
0 |
T17 |
121545 |
16333 |
0 |
0 |
T18 |
2336 |
2181 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
502534067 |
498440019 |
0 |
0 |
T1 |
200736 |
200552 |
0 |
0 |
T2 |
249751 |
249611 |
0 |
0 |
T4 |
32274 |
4020 |
0 |
0 |
T5 |
84950 |
5853 |
0 |
0 |
T6 |
5047 |
4893 |
0 |
0 |
T7 |
4358 |
4231 |
0 |
0 |
T15 |
4905 |
4764 |
0 |
0 |
T16 |
1371 |
1130 |
0 |
0 |
T17 |
121545 |
16333 |
0 |
0 |
T18 |
2336 |
2181 |
0 |
0 |