Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T1
0	1	Unreachable
1	0	Covered	T4,T5,T17

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	153051899	150747157	0	0
AllClkBypReqTrue_A	153051899	134945	0	0
IoClkBypReqFalse_A	153051899	150661003	0	2415
IoClkBypReqTrue_A	153051899	216771	0	0
LcClkBypAckFalse_A	153051899	150757782	0	0
LcClkBypAckTrue_A	153051899	124320	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153051899	150747157	0	0
T1	126464	126348	0	0
T2	44954	44928	0	0
T4	27755	3455	0	0
T5	42475	2925	0	0
T6	1210	1173	0	0
T7	1088	1056	0	0
T15	1225	998	0	0
T16	1445	1211	0	0
T17	24308	3265	0	0
T18	2336	1934	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153051899	134945	0	0
T2	44954	0	0	0
T4	27755	0	0	0
T5	42475	0	0	0
T15	1225	192	0	0
T16	1445	0	0	0
T17	24308	0	0	0
T18	2336	246	0	0
T19	1777	0	0	0
T20	2269	9	0	0
T24	1310	0	0	0
T40	0	81	0	0
T41	0	154	0	0
T74	0	274	0	0
T86	0	197	0	0
T127	0	79	0	0
T128	0	213	0	0
T129	0	85	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153051899	150661003	0	2415
T1	126464	126346	0	3
T2	44954	44926	0	3
T4	27755	3443	0	3
T5	42475	2897	0	3
T6	1210	1171	0	3
T7	1088	1054	0	3
T15	1225	940	0	3
T16	1445	1209	0	3
T17	24308	3227	0	3
T18	2336	1805	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153051899	216771	0	0
T2	44954	0	0	0
T4	27755	0	0	0
T5	42475	0	0	0
T15	1225	248	0	0
T16	1445	0	0	0
T17	24308	0	0	0
T18	2336	373	0	0
T19	1777	0	0	0
T20	2269	538	0	0
T24	1310	0	0	0
T40	0	67	0	0
T41	0	223	0	0
T74	0	84	0	0
T86	0	212	0	0
T127	0	124	0	0
T128	0	217	0	0
T129	0	25	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153051899	150757782	0	0
T1	126464	126348	0	0
T2	44954	44928	0	0
T4	27755	3455	0	0
T5	42475	2925	0	0
T6	1210	1173	0	0
T7	1088	1056	0	0
T15	1225	1136	0	0
T16	1445	1211	0	0
T17	24308	3265	0	0
T18	2336	2004	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153051899	124320	0	0
T2	44954	0	0	0
T4	27755	0	0	0
T5	42475	0	0	0
T8	0	1969	0	0
T15	1225	54	0	0
T16	1445	0	0	0
T17	24308	0	0	0
T18	2336	176	0	0
T19	1777	0	0	0
T20	2269	127	0	0
T24	1310	0	0	0
T40	0	20	0	0
T41	0	137	0	0
T74	0	5	0	0
T86	0	78	0	0
T127	0	78	0	0
T128	0	52	0	0