Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	2010137944	16440	0	0
TransStop_A	2010137944	8434	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2010137944	16440	0	0
T1	802944	0	0	0
T2	999004	0	0	0
T4	129096	0	0	0
T5	339804	0	0	0
T6	20192	4	0	0
T7	17432	0	0	0
T8	0	217	0	0
T15	19620	0	0	0
T16	5484	0	0	0
T17	486184	0	0	0
T18	9348	0	0	0
T19	0	10	0	0
T39	0	4	0	0
T42	0	4	0	0
T80	0	4	0	0
T81	0	41	0	0
T83	0	26	0	0
T84	0	24	0	0
T85	0	3	0	0
T130	0	6	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2010137944	8434	0	0
T1	802944	0	0	0
T2	999004	0	0	0
T4	129096	0	0	0
T5	339804	0	0	0
T6	20192	4	0	0
T7	17432	0	0	0
T8	0	121	0	0
T15	19620	0	0	0
T16	5484	0	0	0
T17	486184	0	0	0
T18	9348	0	0	0
T19	0	7	0	0
T39	0	4	0	0
T42	0	4	0	0
T80	0	4	0	0
T81	0	20	0	0
T83	0	6	0	0
T84	0	6	0	0
T85	0	10	0	0
T130	0	2	0	0
T131	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	502534486	4100	0	0
TransStop_A	502534486	2144	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502534486	4100	0	0
T1	200736	0	0	0
T2	249751	0	0	0
T4	32274	0	0	0
T5	84951	0	0	0
T6	5048	1	0	0
T7	4358	0	0	0
T8	0	55	0	0
T15	4905	0	0	0
T16	1371	0	0	0
T17	121546	0	0	0
T18	2337	0	0	0
T19	0	2	0	0
T39	0	1	0	0
T42	0	1	0	0
T80	0	1	0	0
T81	0	11	0	0
T83	0	8	0	0
T84	0	5	0	0
T130	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502534486	2144	0	0
T1	200736	0	0	0
T2	249751	0	0	0
T4	32274	0	0	0
T5	84951	0	0	0
T6	5048	1	0	0
T7	4358	0	0	0
T8	0	33	0	0
T15	4905	0	0	0
T16	1371	0	0	0
T17	121546	0	0	0
T18	2337	0	0	0
T19	0	1	0	0
T39	0	1	0	0
T42	0	1	0	0
T80	0	1	0	0
T81	0	5	0	0
T83	0	2	0	0
T84	0	1	0	0
T85	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	502534486	4155	0	0
TransStop_A	502534486	2189	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502534486	4155	0	0
T1	200736	0	0	0
T2	249751	0	0	0
T4	32274	0	0	0
T5	84951	0	0	0
T6	5048	1	0	0
T7	4358	0	0	0
T8	0	50	0	0
T15	4905	0	0	0
T16	1371	0	0	0
T17	121546	0	0	0
T18	2337	0	0	0
T19	0	2	0	0
T39	0	1	0	0
T42	0	1	0	0
T80	0	1	0	0
T81	0	13	0	0
T83	0	5	0	0
T84	0	5	0	0
T85	0	3	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502534486	2189	0	0
T1	200736	0	0	0
T2	249751	0	0	0
T4	32274	0	0	0
T5	84951	0	0	0
T6	5048	1	0	0
T7	4358	0	0	0
T8	0	22	0	0
T15	4905	0	0	0
T16	1371	0	0	0
T17	121546	0	0	0
T18	2337	0	0	0
T19	0	2	0	0
T39	0	1	0	0
T42	0	1	0	0
T80	0	1	0	0
T81	0	6	0	0
T84	0	2	0	0
T85	0	2	0	0
T131	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	502534486	4115	0	0
TransStop_A	502534486	2051	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502534486	4115	0	0
T1	200736	0	0	0
T2	249751	0	0	0
T4	32274	0	0	0
T5	84951	0	0	0
T6	5048	1	0	0
T7	4358	0	0	0
T8	0	56	0	0
T15	4905	0	0	0
T16	1371	0	0	0
T17	121546	0	0	0
T18	2337	0	0	0
T19	0	3	0	0
T39	0	1	0	0
T42	0	1	0	0
T80	0	1	0	0
T81	0	10	0	0
T83	0	7	0	0
T84	0	10	0	0
T130	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502534486	2051	0	0
T1	200736	0	0	0
T2	249751	0	0	0
T4	32274	0	0	0
T5	84951	0	0	0
T6	5048	1	0	0
T7	4358	0	0	0
T8	0	30	0	0
T15	4905	0	0	0
T16	1371	0	0	0
T17	121546	0	0	0
T18	2337	0	0	0
T19	0	3	0	0
T39	0	1	0	0
T42	0	1	0	0
T80	0	1	0	0
T81	0	6	0	0
T83	0	2	0	0
T84	0	2	0	0
T130	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	502534486	4070	0	0
TransStop_A	502534486	2050	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502534486	4070	0	0
T1	200736	0	0	0
T2	249751	0	0	0
T4	32274	0	0	0
T5	84951	0	0	0
T6	5048	1	0	0
T7	4358	0	0	0
T8	0	56	0	0
T15	4905	0	0	0
T16	1371	0	0	0
T17	121546	0	0	0
T18	2337	0	0	0
T19	0	3	0	0
T39	0	1	0	0
T42	0	1	0	0
T80	0	1	0	0
T81	0	7	0	0
T83	0	6	0	0
T84	0	4	0	0
T130	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502534486	2050	0	0
T1	200736	0	0	0
T2	249751	0	0	0
T4	32274	0	0	0
T5	84951	0	0	0
T6	5048	1	0	0
T7	4358	0	0	0
T8	0	36	0	0
T15	4905	0	0	0
T16	1371	0	0	0
T17	121546	0	0	0
T18	2337	0	0	0
T19	0	1	0	0
T39	0	1	0	0
T42	0	1	0	0
T80	0	1	0	0
T81	0	3	0	0
T83	0	2	0	0
T84	0	1	0	0
T85	0	3	0	0