Module Definition
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Module : prim_generic_clock_mux2
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_div2.u_step_down_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT6,T7,T1
01CoveredT6,T7,T1
10CoveredT15,T18,T20 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT6,T7,T1
10CoveredT15,T18,T20
11CoveredT15,T18,T20 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT15,T18,T20
10CoveredT6,T7,T1
11CoveredT6,T7,T1
Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 590281462 590279047 0 0
selKnown1 1414988169 1414985754 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 590281462 590279047 0 0
T1 240810 240807 0 0
T2 299575 299572 0 0
T4 24798 24795 0 0
T5 49682 49679 0 0
T6 5992 5989 0 0
T7 5112 5109 0 0
T15 5972 5969 0 0
T16 1480 1477 0 0
T17 82149 82146 0 0
T18 2993 2990 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1414988169 1414985754 0 0
T1 578100 578097 0 0
T2 719262 719259 0 0
T4 92946 92943 0 0
T5 244650 244647 0 0
T6 14538 14535 0 0
T7 12546 12543 0 0
T15 14124 14121 0 0
T16 3912 3909 0 0
T17 350040 350037 0 0
T18 6729 6726 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT6,T7,T1
01CoveredT6,T7,T1
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT6,T7,T1
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT6,T7,T1
11CoveredT6,T7,T1
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 236949594 236948789 0 0
selKnown1 471662723 471661918 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 236949594 236948789 0 0
T1 96324 96323 0 0
T2 119830 119829 0 0
T4 9919 9918 0 0
T5 19873 19872 0 0
T6 2397 2396 0 0
T7 2045 2044 0 0
T15 2434 2433 0 0
T16 592 591 0 0
T17 32859 32858 0 0
T18 1285 1284 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 471662723 471661918 0 0
T1 192700 192699 0 0
T2 239754 239753 0 0
T4 30982 30981 0 0
T5 81550 81549 0 0
T6 4846 4845 0 0
T7 4182 4181 0 0
T15 4708 4707 0 0
T16 1304 1303 0 0
T17 116680 116679 0 0
T18 2243 2242 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT6,T7,T1
01CoveredT6,T7,T1
10CoveredT15,T18,T20 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT6,T7,T1
10CoveredT15,T18,T20
11CoveredT15,T18,T20 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT15,T18,T20
10CoveredT6,T7,T1
11CoveredT6,T7,T1
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 234857712 234856907 0 0
selKnown1 471662723 471661918 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 234857712 234856907 0 0
T1 96324 96323 0 0
T2 119830 119829 0 0
T4 9919 9918 0 0
T5 19873 19872 0 0
T6 2397 2396 0 0
T7 2045 2044 0 0
T15 2321 2320 0 0
T16 592 591 0 0
T17 32859 32858 0 0
T18 1068 1067 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 471662723 471661918 0 0
T1 192700 192699 0 0
T2 239754 239753 0 0
T4 30982 30981 0 0
T5 81550 81549 0 0
T6 4846 4845 0 0
T7 4182 4181 0 0
T15 4708 4707 0 0
T16 1304 1303 0 0
T17 116680 116679 0 0
T18 2243 2242 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT6,T7,T1
01CoveredT6,T7,T1
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT6,T7,T1
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT6,T7,T1
11CoveredT6,T7,T1
Assert Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 118474156 118473351 0 0
selKnown1 471662723 471661918 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 118474156 118473351 0 0
T1 48162 48161 0 0
T2 59915 59914 0 0
T4 4960 4959 0 0
T5 9936 9935 0 0
T6 1198 1197 0 0
T7 1022 1021 0 0
T15 1217 1216 0 0
T16 296 295 0 0
T17 16431 16430 0 0
T18 640 639 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 471662723 471661918 0 0
T1 192700 192699 0 0
T2 239754 239753 0 0
T4 30982 30981 0 0
T5 81550 81549 0 0
T6 4846 4845 0 0
T7 4182 4181 0 0
T15 4708 4707 0 0
T16 1304 1303 0 0
T17 116680 116679 0 0
T18 2243 2242 0 0

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