Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	153051899	15108872	0	60

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153051899	15108872	0	60
T1	126464	46458	0	1
T2	44954	9221	0	1
T3	0	12153	0	1
T4	27755	0	0	0
T5	42475	0	0	0
T8	0	69586	0	0
T9	0	118544	0	0
T10	0	189463	0	0
T11	0	7578	0	1
T12	0	170075	0	0
T13	0	11356	0	1
T15	1225	0	0	0
T16	1445	0	0	0
T17	24308	0	0	0
T18	2336	0	0	0
T19	1777	0	0	0
T20	2269	0	0	0
T22	0	831	0	1
T23	0	0	0	1
T88	0	0	0	1
T132	0	0	0	1
T133	0	0	0	1