Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	153997631	4912510	0	0
clk_enables_rd_A	153997631	35826	0	0
clk_hints_rd_A	153997631	31496	0	0
extclk_ctrl_rd_A	153997631	40335	0	0
extclk_ctrl_regwen_rd_A	153997631	30180	0	0
jitter_enable_rd_A	153997631	46969	0	0
jitter_regwen_rd_A	153997631	33307	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153997631	4912510	0	0
T8	166603	57712	0	0
T10	0	114563	0	0
T12	0	105072	0	0
T14	0	87387	0	0
T30	0	164534	0	0
T31	116432	0	0	0
T34	229481	0	0	0
T36	0	85578	0	0
T75	0	135453	0	0
T76	0	101470	0	0
T77	0	76390	0	0
T78	0	121154	0	0
T79	1464	0	0	0
T80	1266	0	0	0
T81	3859	0	0	0
T82	43643	0	0	0
T83	1731	0	0	0
T84	3171	0	0	0
T85	2210	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153997631	35826	0	0
T3	99766	0	0	0
T14	0	1902	0	0
T29	21318	0	0	0
T39	1960	1	0	0
T42	1716	0	0	0
T77	0	2947	0	0
T86	2200	0	0	0
T128	1473	0	0	0
T129	1401	0	0	0
T130	1279	0	0	0
T150	0	2	0	0
T151	0	4	0	0
T152	0	1	0	0
T153	0	939	0	0
T154	0	10	0	0
T155	0	735	0	0
T156	0	6	0	0
T157	1136	0	0	0
T158	2098	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153997631	31496	0	0
T3	99766	0	0	0
T14	0	1607	0	0
T29	21318	0	0	0
T39	1960	2	0	0
T42	1716	5	0	0
T77	0	2648	0	0
T86	2200	0	0	0
T128	1473	0	0	0
T129	1401	0	0	0
T130	1279	0	0	0
T150	0	1	0	0
T151	0	7	0	0
T152	0	3	0	0
T153	0	871	0	0
T154	0	4	0	0
T157	1136	0	0	0
T158	2098	0	0	0
T159	0	4	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153997631	40335	0	0
T2	44954	0	0	0
T4	27755	22	0	0
T5	42475	0	0	0
T14	0	2115	0	0
T15	1225	19	0	0
T16	1445	0	0	0
T17	24308	0	0	0
T18	2336	0	0	0
T19	1777	0	0	0
T20	2269	0	0	0
T24	1310	0	0	0
T41	0	23	0	0
T74	0	83	0	0
T86	0	36	0	0
T160	0	141	0	0
T161	0	3	0	0
T162	0	39	0	0
T163	0	30	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153997631	30180	0	0
T2	44954	0	0	0
T4	27755	12	0	0
T5	42475	0	0	0
T14	0	1730	0	0
T16	1445	0	0	0
T17	24308	0	0	0
T18	2336	0	0	0
T19	1777	0	0	0
T20	2269	0	0	0
T24	1310	0	0	0
T25	1217	0	0	0
T77	0	2621	0	0
T153	0	739	0	0
T155	0	691	0	0
T160	0	72	0	0
T164	0	4	0	0
T165	0	28	0	0
T166	0	6	0	0
T167	0	1733	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153997631	46969	0	0
T3	99766	0	0	0
T14	0	2382	0	0
T29	21318	0	0	0
T39	1960	102	0	0
T42	1716	108	0	0
T77	0	4046	0	0
T86	2200	0	0	0
T128	1473	0	0	0
T129	1401	0	0	0
T130	1279	0	0	0
T150	0	90	0	0
T151	0	228	0	0
T152	0	109	0	0
T157	1136	0	0	0
T158	2098	0	0	0
T159	0	113	0	0
T168	0	110	0	0
T169	0	59	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153997631	33307	0	0
T14	270071	1775	0	0
T23	80182	0	0	0
T30	339353	0	0	0
T58	0	903	0	0
T77	0	2882	0	0
T87	44056	0	0	0
T153	0	807	0	0
T155	0	991	0	0
T167	0	1850	0	0
T170	0	2428	0	0
T171	0	2395	0	0
T172	0	4611	0	0
T173	0	2639	0	0
T174	2092	0	0	0
T175	886	0	0	0
T176	3857	0	0	0
T177	1334	0	0	0
T178	1685	0	0	0
T179	3068	0	0	0