Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	100.00	86.67			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_io_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T1
0	1	Covered	T4,T5,T17
1	0	Covered	T1,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T1
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T1
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T1
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T6,T7,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T1
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T6,T7,T1

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1539976310	1448274	0	0
DstReqKnown_A	2147483647	2147483647	0	0
SrcAckBusyChk_A	1539976310	281235	0	0
SrcBusyKnown_A	1539976310	1517163180	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1539976310	1448274	0	0
T1	1264640	1957	0	0
T2	449540	1335	0	0
T3	0	1706	0	0
T4	277550	1110	0	0
T5	424750	1828	0	0
T15	12250	0	0	0
T16	14450	0	0	0
T17	243080	1669	0	0
T18	23360	0	0	0
T19	17770	0	0	0
T20	22690	0	0	0
T21	0	1747	0	0
T22	0	194	0	0
T28	0	1593	0	0
T29	0	1362	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1268554	1267472	0	0
T2	1578264	1577518	0	0
T4	187254	25408	0	0
T5	474170	37000	0	0
T6	31820	30924	0	0
T7	27396	26738	0	0
T15	31236	30446	0	0
T16	8472	7136	0	0
T17	691714	103244	0	0
T18	15250	14432	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1539976310	281235	0	0
T1	1264640	340	0	0
T2	449540	420	0	0
T3	0	360	0	0
T4	277550	144	0	0
T5	424750	364	0	0
T15	12250	0	0	0
T16	14450	0	0	0
T17	243080	504	0	0
T18	23360	0	0	0
T19	17770	0	0	0
T20	22690	0	0	0
T21	0	492	0	0
T22	0	60	0	0
T28	0	340	0	0
T29	0	364	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1539976310	1517163180	0	0
T1	1264640	1263490	0	0
T2	449540	449290	0	0
T4	277550	34610	0	0
T5	424750	29390	0	0
T6	12100	11740	0	0
T7	10880	10570	0	0
T15	12250	11910	0	0
T16	14450	12120	0	0
T17	243080	32840	0	0
T18	23360	21810	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T1
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T1
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T1
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T1
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T6,T7,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T1
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T6,T7,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	153997631	90431	0	0
DstReqKnown_A	474460964	470407552	0	0
SrcAckBusyChk_A	153997631	25247	0	0
SrcBusyKnown_A	153997631	151716318	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153997631	90431	0	0
T1	126464	131	0	0
T2	44954	106	0	0
T3	0	121	0	0
T4	27755	46	0	0
T5	42475	89	0	0
T15	1225	0	0	0
T16	1445	0	0	0
T17	24308	89	0	0
T18	2336	0	0	0
T19	1777	0	0	0
T20	2269	0	0	0
T21	0	86	0	0
T22	0	15	0	0
T28	0	114	0	0
T29	0	69	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474460964	470407552	0	0
T1	192700	192524	0	0
T2	239754	239619	0	0
T4	30982	3859	0	0
T5	81550	5620	0	0
T6	4846	4697	0	0
T7	4182	4061	0	0
T15	4708	4573	0	0
T16	1304	1074	0	0
T17	116680	15680	0	0
T18	2243	2094	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153997631	25247	0	0
T1	126464	34	0	0
T2	44954	42	0	0
T3	0	36	0	0
T4	27755	10	0	0
T5	42475	26	0	0
T15	1225	0	0	0
T16	1445	0	0	0
T17	24308	36	0	0
T18	2336	0	0	0
T19	1777	0	0	0
T20	2269	0	0	0
T21	0	34	0	0
T22	0	6	0	0
T28	0	34	0	0
T29	0	26	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153997631	151716318	0	0
T1	126464	126349	0	0
T2	44954	44929	0	0
T4	27755	3461	0	0
T5	42475	2939	0	0
T6	1210	1174	0	0
T7	1088	1057	0	0
T15	1225	1191	0	0
T16	1445	1212	0	0
T17	24308	3284	0	0
T18	2336	2181	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T1
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T1
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T1
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T1
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T6,T7,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T1
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T6,T7,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	153997631	129502	0	0
DstReqKnown_A	238301090	237295709	0	0
SrcAckBusyChk_A	153997631	25247	0	0
SrcBusyKnown_A	153997631	151716318	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153997631	129502	0	0
T1	126464	193	0	0
T2	44954	134	0	0
T3	0	170	0	0
T4	27755	72	0	0
T5	42475	127	0	0
T15	1225	0	0	0
T16	1445	0	0	0
T17	24308	115	0	0
T18	2336	0	0	0
T19	1777	0	0	0
T20	2269	0	0	0
T21	0	125	0	0
T22	0	20	0	0
T28	0	159	0	0
T29	0	95	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238301090	237295709	0	0
T1	96324	96262	0	0
T2	119830	119809	0	0
T4	9919	1930	0	0
T5	19873	2812	0	0
T6	2397	2349	0	0
T7	2045	2031	0	0
T15	2434	2399	0	0
T16	592	537	0	0
T17	32859	7844	0	0
T18	1285	1264	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153997631	25247	0	0
T1	126464	34	0	0
T2	44954	42	0	0
T3	0	36	0	0
T4	27755	10	0	0
T5	42475	26	0	0
T15	1225	0	0	0
T16	1445	0	0	0
T17	24308	36	0	0
T18	2336	0	0	0
T19	1777	0	0	0
T20	2269	0	0	0
T21	0	34	0	0
T22	0	6	0	0
T28	0	34	0	0
T29	0	26	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153997631	151716318	0	0
T1	126464	126349	0	0
T2	44954	44929	0	0
T4	27755	3461	0	0
T5	42475	2939	0	0
T6	1210	1174	0	0
T7	1088	1057	0	0
T15	1225	1191	0	0
T16	1445	1212	0	0
T17	24308	3284	0	0
T18	2336	2181	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T1
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T1
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T1
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T1
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T6,T7,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T1
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T6,T7,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	153997631	206431	0	0
DstReqKnown_A	119149904	118647333	0	0
SrcAckBusyChk_A	153997631	25247	0	0
SrcBusyKnown_A	153997631	151716318	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153997631	206431	0	0
T1	126464	327	0	0
T2	44954	179	0	0
T3	0	267	0	0
T4	27755	127	0	0
T5	42475	209	0	0
T15	1225	0	0	0
T16	1445	0	0	0
T17	24308	162	0	0
T18	2336	0	0	0
T19	1777	0	0	0
T20	2269	0	0	0
T21	0	174	0	0
T22	0	27	0	0
T28	0	246	0	0
T29	0	138	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119149904	118647333	0	0
T1	48162	48131	0	0
T2	59915	59905	0	0
T4	4960	966	0	0
T5	9936	1406	0	0
T6	1198	1174	0	0
T7	1022	1015	0	0
T15	1217	1200	0	0
T16	296	269	0	0
T17	16431	3924	0	0
T18	640	630	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153997631	25247	0	0
T1	126464	34	0	0
T2	44954	42	0	0
T3	0	36	0	0
T4	27755	10	0	0
T5	42475	26	0	0
T15	1225	0	0	0
T16	1445	0	0	0
T17	24308	36	0	0
T18	2336	0	0	0
T19	1777	0	0	0
T20	2269	0	0	0
T21	0	34	0	0
T22	0	6	0	0
T28	0	34	0	0
T29	0	26	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153997631	151716318	0	0
T1	126464	126349	0	0
T2	44954	44929	0	0
T4	27755	3461	0	0
T5	42475	2939	0	0
T6	1210	1174	0	0
T7	1088	1057	0	0
T15	1225	1191	0	0
T16	1445	1212	0	0
T17	24308	3284	0	0
T18	2336	2181	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T1
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T1
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T1
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T1
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T6,T7,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T1
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T6,T7,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	153997631	88703	0	0
DstReqKnown_A	505449004	501157732	0	0
SrcAckBusyChk_A	153997631	25247	0	0
SrcBusyKnown_A	153997631	151716318	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153997631	88703	0	0
T1	126464	126	0	0
T2	44954	106	0	0
T3	0	119	0	0
T4	27755	46	0	0
T5	42475	88	0	0
T15	1225	0	0	0
T16	1445	0	0	0
T17	24308	89	0	0
T18	2336	0	0	0
T19	1777	0	0	0
T20	2269	0	0	0
T21	0	85	0	0
T22	0	15	0	0
T28	0	113	0	0
T29	0	69	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505449004	501157732	0	0
T1	200736	200552	0	0
T2	249751	249611	0	0
T4	32274	4020	0	0
T5	84950	5853	0	0
T6	5047	4893	0	0
T7	4358	4231	0	0
T15	4905	4764	0	0
T16	1371	1130	0	0
T17	121545	16333	0	0
T18	2336	2181	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153997631	25247	0	0
T1	126464	34	0	0
T2	44954	42	0	0
T3	0	36	0	0
T4	27755	10	0	0
T5	42475	26	0	0
T15	1225	0	0	0
T16	1445	0	0	0
T17	24308	36	0	0
T18	2336	0	0	0
T19	1777	0	0	0
T20	2269	0	0	0
T21	0	34	0	0
T22	0	6	0	0
T28	0	34	0	0
T29	0	26	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153997631	151716318	0	0
T1	126464	126349	0	0
T2	44954	44929	0	0
T4	27755	3461	0	0
T5	42475	2939	0	0
T6	1210	1174	0	0
T7	1088	1057	0	0
T15	1225	1191	0	0
T16	1445	1212	0	0
T17	24308	3284	0	0
T18	2336	2181	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T1
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T1
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T1
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T1
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T6,T7,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T1
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T6,T7,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	153997631	128895	0	0
DstReqKnown_A	242590545	240541590	0	0
SrcAckBusyChk_A	153997631	24819	0	0
SrcBusyKnown_A	153997631	151716318	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153997631	128895	0	0
T1	126464	196	0	0
T2	44954	133	0	0
T3	0	172	0	0
T4	27755	51	0	0
T5	42475	73	0	0
T15	1225	0	0	0
T16	1445	0	0	0
T17	24308	77	0	0
T18	2336	0	0	0
T19	1777	0	0	0
T20	2269	0	0	0
T21	0	76	0	0
T22	0	20	0	0
T28	0	160	0	0
T29	0	60	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	242590545	240541590	0	0
T1	96355	96267	0	0
T2	119882	119815	0	0
T4	15492	1929	0	0
T5	40776	2809	0	0
T6	2422	2349	0	0
T7	2091	2031	0	0
T15	2354	2287	0	0
T16	673	558	0	0
T17	58342	7841	0	0
T18	1121	1047	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153997631	24819	0	0
T1	126464	34	0	0
T2	44954	42	0	0
T3	0	36	0	0
T4	27755	5	0	0
T5	42475	13	0	0
T15	1225	0	0	0
T16	1445	0	0	0
T17	24308	18	0	0
T18	2336	0	0	0
T19	1777	0	0	0
T20	2269	0	0	0
T21	0	17	0	0
T22	0	6	0	0
T28	0	34	0	0
T29	0	13	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153997631	151716318	0	0
T1	126464	126349	0	0
T2	44954	44929	0	0
T4	27755	3461	0	0
T5	42475	2939	0	0
T6	1210	1174	0	0
T7	1088	1057	0	0
T15	1225	1191	0	0
T16	1445	1212	0	0
T17	24308	3284	0	0
T18	2336	2181	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T1
0	1	Covered	T4,T5,T17
1	0	Covered	T1,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T1
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T1
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T1
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T6,T7,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T1
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T6,T7,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	153997631	112073	0	0
DstReqKnown_A	474460964	470407552	0	0
SrcAckBusyChk_A	153997631	31082	0	0
SrcBusyKnown_A	153997631	151716318	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153997631	112073	0	0
T1	126464	129	0	0
T2	44954	108	0	0
T3	0	122	0	0
T4	27755	96	0	0
T5	42475	178	0	0
T15	1225	0	0	0
T16	1445	0	0	0
T17	24308	177	0	0
T18	2336	0	0	0
T19	1777	0	0	0
T20	2269	0	0	0
T21	0	180	0	0
T22	0	15	0	0
T28	0	116	0	0
T29	0	139	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474460964	470407552	0	0
T1	192700	192524	0	0
T2	239754	239619	0	0
T4	30982	3859	0	0
T5	81550	5620	0	0
T6	4846	4697	0	0
T7	4182	4061	0	0
T15	4708	4573	0	0
T16	1304	1074	0	0
T17	116680	15680	0	0
T18	2243	2094	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153997631	31082	0	0
T1	126464	34	0	0
T2	44954	42	0	0
T3	0	36	0	0
T4	27755	20	0	0
T5	42475	52	0	0
T15	1225	0	0	0
T16	1445	0	0	0
T17	24308	72	0	0
T18	2336	0	0	0
T19	1777	0	0	0
T20	2269	0	0	0
T21	0	68	0	0
T22	0	6	0	0
T28	0	34	0	0
T29	0	52	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153997631	151716318	0	0
T1	126464	126349	0	0
T2	44954	44929	0	0
T4	27755	3461	0	0
T5	42475	2939	0	0
T6	1210	1174	0	0
T7	1088	1057	0	0
T15	1225	1191	0	0
T16	1445	1212	0	0
T17	24308	3284	0	0
T18	2336	2181	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T1
0	1	Covered	T4,T5,T17
1	0	Covered	T1,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T1
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T1
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T1
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T6,T7,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T1
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T6,T7,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	153997631	161240	0	0
DstReqKnown_A	238301090	237295709	0	0
SrcAckBusyChk_A	153997631	31130	0	0
SrcBusyKnown_A	153997631	151716318	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153997631	161240	0	0
T1	126464	198	0	0
T2	44954	141	0	0
T3	0	171	0	0
T4	27755	157	0	0
T5	42475	251	0	0
T15	1225	0	0	0
T16	1445	0	0	0
T17	24308	237	0	0
T18	2336	0	0	0
T19	1777	0	0	0
T20	2269	0	0	0
T21	0	245	0	0
T22	0	20	0	0
T28	0	161	0	0
T29	0	191	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238301090	237295709	0	0
T1	96324	96262	0	0
T2	119830	119809	0	0
T4	9919	1930	0	0
T5	19873	2812	0	0
T6	2397	2349	0	0
T7	2045	2031	0	0
T15	2434	2399	0	0
T16	592	537	0	0
T17	32859	7844	0	0
T18	1285	1264	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153997631	31130	0	0
T1	126464	34	0	0
T2	44954	42	0	0
T3	0	36	0	0
T4	27755	20	0	0
T5	42475	52	0	0
T15	1225	0	0	0
T16	1445	0	0	0
T17	24308	72	0	0
T18	2336	0	0	0
T19	1777	0	0	0
T20	2269	0	0	0
T21	0	68	0	0
T22	0	6	0	0
T28	0	34	0	0
T29	0	52	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153997631	151716318	0	0
T1	126464	126349	0	0
T2	44954	44929	0	0
T4	27755	3461	0	0
T5	42475	2939	0	0
T6	1210	1174	0	0
T7	1088	1057	0	0
T15	1225	1191	0	0
T16	1445	1212	0	0
T17	24308	3284	0	0
T18	2336	2181	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T1
0	1	Covered	T4,T5,T17
1	0	Covered	T1,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T1
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T1
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T1
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T6,T7,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T1
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T6,T7,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	153997631	258154	0	0
DstReqKnown_A	119149904	118647333	0	0
SrcAckBusyChk_A	153997631	31117	0	0
SrcBusyKnown_A	153997631	151716318	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153997631	258154	0	0
T1	126464	332	0	0
T2	44954	180	0	0
T3	0	274	0	0
T4	27755	267	0	0
T5	42475	409	0	0
T15	1225	0	0	0
T16	1445	0	0	0
T17	24308	316	0	0
T18	2336	0	0	0
T19	1777	0	0	0
T20	2269	0	0	0
T21	0	353	0	0
T22	0	28	0	0
T28	0	253	0	0
T29	0	278	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119149904	118647333	0	0
T1	48162	48131	0	0
T2	59915	59905	0	0
T4	4960	966	0	0
T5	9936	1406	0	0
T6	1198	1174	0	0
T7	1022	1015	0	0
T15	1217	1200	0	0
T16	296	269	0	0
T17	16431	3924	0	0
T18	640	630	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153997631	31117	0	0
T1	126464	34	0	0
T2	44954	42	0	0
T3	0	36	0	0
T4	27755	20	0	0
T5	42475	52	0	0
T15	1225	0	0	0
T16	1445	0	0	0
T17	24308	72	0	0
T18	2336	0	0	0
T19	1777	0	0	0
T20	2269	0	0	0
T21	0	68	0	0
T22	0	6	0	0
T28	0	34	0	0
T29	0	52	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153997631	151716318	0	0
T1	126464	126349	0	0
T2	44954	44929	0	0
T4	27755	3461	0	0
T5	42475	2939	0	0
T6	1210	1174	0	0
T7	1088	1057	0	0
T15	1225	1191	0	0
T16	1445	1212	0	0
T17	24308	3284	0	0
T18	2336	2181	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T1
0	1	Covered	T4,T5,T17
1	0	Covered	T1,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T1
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T1
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T1
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T6,T7,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T1
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T6,T7,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	153997631	110667	0	0
DstReqKnown_A	505449004	501157732	0	0
SrcAckBusyChk_A	153997631	31138	0	0
SrcBusyKnown_A	153997631	151716318	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153997631	110667	0	0
T1	126464	129	0	0
T2	44954	108	0	0
T3	0	120	0	0
T4	27755	93	0	0
T5	42475	174	0	0
T15	1225	0	0	0
T16	1445	0	0	0
T17	24308	177	0	0
T18	2336	0	0	0
T19	1777	0	0	0
T20	2269	0	0	0
T21	0	174	0	0
T22	0	15	0	0
T28	0	112	0	0
T29	0	139	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505449004	501157732	0	0
T1	200736	200552	0	0
T2	249751	249611	0	0
T4	32274	4020	0	0
T5	84950	5853	0	0
T6	5047	4893	0	0
T7	4358	4231	0	0
T15	4905	4764	0	0
T16	1371	1130	0	0
T17	121545	16333	0	0
T18	2336	2181	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153997631	31138	0	0
T1	126464	34	0	0
T2	44954	42	0	0
T3	0	36	0	0
T4	27755	20	0	0
T5	42475	52	0	0
T15	1225	0	0	0
T16	1445	0	0	0
T17	24308	72	0	0
T18	2336	0	0	0
T19	1777	0	0	0
T20	2269	0	0	0
T21	0	68	0	0
T22	0	6	0	0
T28	0	34	0	0
T29	0	52	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153997631	151716318	0	0
T1	126464	126349	0	0
T2	44954	44929	0	0
T4	27755	3461	0	0
T5	42475	2939	0	0
T6	1210	1174	0	0
T7	1088	1057	0	0
T15	1225	1191	0	0
T16	1445	1212	0	0
T17	24308	3284	0	0
T18	2336	2181	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T1
0	1	Covered	T4,T5,T17
1	0	Covered	T1,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T1
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T1
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T1
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T6,T7,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T1
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T6,T7,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	153997631	162178	0	0
DstReqKnown_A	242590545	240541590	0	0
SrcAckBusyChk_A	153997631	30961	0	0
SrcBusyKnown_A	153997631	151716318	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153997631	162178	0	0
T1	126464	196	0	0
T2	44954	140	0	0
T3	0	170	0	0
T4	27755	155	0	0
T5	42475	230	0	0
T15	1225	0	0	0
T16	1445	0	0	0
T17	24308	230	0	0
T18	2336	0	0	0
T19	1777	0	0	0
T20	2269	0	0	0
T21	0	249	0	0
T22	0	19	0	0
T28	0	159	0	0
T29	0	184	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	242590545	240541590	0	0
T1	96355	96267	0	0
T2	119882	119815	0	0
T4	15492	1929	0	0
T5	40776	2809	0	0
T6	2422	2349	0	0
T7	2091	2031	0	0
T15	2354	2287	0	0
T16	673	558	0	0
T17	58342	7841	0	0
T18	1121	1047	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153997631	30961	0	0
T1	126464	34	0	0
T2	44954	42	0	0
T3	0	36	0	0
T4	27755	19	0	0
T5	42475	39	0	0
T15	1225	0	0	0
T16	1445	0	0	0
T17	24308	54	0	0
T18	2336	0	0	0
T19	1777	0	0	0
T20	2269	0	0	0
T21	0	67	0	0
T22	0	6	0	0
T28	0	34	0	0
T29	0	39	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153997631	151716318	0	0
T1	126464	126349	0	0
T2	44954	44929	0	0
T4	27755	3461	0	0
T5	42475	2939	0	0
T6	1210	1174	0	0
T7	1088	1057	0	0
T15	1225	1191	0	0
T16	1445	1212	0	0
T17	24308	3284	0	0
T18	2336	2181	0	0