Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	459155697	468	0	0
StatusRise_A	459155697	468	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459155697	468	0	0
T2	134862	0	0	0
T16	4335	9	0	0
T17	72924	0	0	0
T18	7008	0	0	0
T19	5331	0	0	0
T20	6807	0	0	0
T21	105321	0	0	0
T24	3930	8	0	0
T25	3651	15	0	0
T26	2769	16	0	0
T157	0	14	0	0
T180	0	17	0	0
T181	0	16	0	0
T182	0	6	0	0
T183	0	3	0	0
T184	0	7	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459155697	468	0	0
T2	134862	0	0	0
T16	4335	9	0	0
T17	72924	0	0	0
T18	7008	0	0	0
T19	5331	0	0	0
T20	6807	0	0	0
T21	105321	0	0	0
T24	3930	8	0	0
T25	3651	15	0	0
T26	2769	16	0	0
T157	0	14	0	0
T180	0	17	0	0
T181	0	16	0	0
T182	0	6	0	0
T183	0	3	0	0
T184	0	7	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	153051899	158	0	0
StatusRise_A	153051899	158	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153051899	158	0	0
T2	44954	0	0	0
T16	1445	3	0	0
T17	24308	0	0	0
T18	2336	0	0	0
T19	1777	0	0	0
T20	2269	0	0	0
T21	35107	0	0	0
T24	1310	2	0	0
T25	1217	6	0	0
T26	923	6	0	0
T157	0	4	0	0
T180	0	6	0	0
T181	0	6	0	0
T182	0	2	0	0
T183	0	1	0	0
T184	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153051899	158	0	0
T2	44954	0	0	0
T16	1445	3	0	0
T17	24308	0	0	0
T18	2336	0	0	0
T19	1777	0	0	0
T20	2269	0	0	0
T21	35107	0	0	0
T24	1310	2	0	0
T25	1217	6	0	0
T26	923	6	0	0
T157	0	4	0	0
T180	0	6	0	0
T181	0	6	0	0
T182	0	2	0	0
T183	0	1	0	0
T184	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	153051899	163	0	0
StatusRise_A	153051899	163	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153051899	163	0	0
T2	44954	0	0	0
T16	1445	3	0	0
T17	24308	0	0	0
T18	2336	0	0	0
T19	1777	0	0	0
T20	2269	0	0	0
T21	35107	0	0	0
T24	1310	4	0	0
T25	1217	5	0	0
T26	923	6	0	0
T157	0	5	0	0
T180	0	5	0	0
T181	0	6	0	0
T182	0	2	0	0
T183	0	1	0	0
T184	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153051899	163	0	0
T2	44954	0	0	0
T16	1445	3	0	0
T17	24308	0	0	0
T18	2336	0	0	0
T19	1777	0	0	0
T20	2269	0	0	0
T21	35107	0	0	0
T24	1310	4	0	0
T25	1217	5	0	0
T26	923	6	0	0
T157	0	5	0	0
T180	0	5	0	0
T181	0	6	0	0
T182	0	2	0	0
T183	0	1	0	0
T184	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	153051899	147	0	0
StatusRise_A	153051899	147	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153051899	147	0	0
T2	44954	0	0	0
T16	1445	3	0	0
T17	24308	0	0	0
T18	2336	0	0	0
T19	1777	0	0	0
T20	2269	0	0	0
T21	35107	0	0	0
T24	1310	2	0	0
T25	1217	4	0	0
T26	923	4	0	0
T157	0	5	0	0
T180	0	6	0	0
T181	0	4	0	0
T182	0	2	0	0
T183	0	1	0	0
T184	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153051899	147	0	0
T2	44954	0	0	0
T16	1445	3	0	0
T17	24308	0	0	0
T18	2336	0	0	0
T19	1777	0	0	0
T20	2269	0	0	0
T21	35107	0	0	0
T24	1310	2	0	0
T25	1217	4	0	0
T26	923	4	0	0
T157	0	5	0	0
T180	0	6	0	0
T181	0	4	0	0
T182	0	2	0	0
T183	0	1	0	0
T184	0	2	0	0