Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T16
1	0	Covered	T6,T7,T1
1	1	Covered	T6,T7,T1

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	51209	0	0
CgEnOn_A	2147483647	42550	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	51209	0	0
T1	1236485	3	0	0
T2	2697098	3	0	0
T4	190449	18	0	0
T5	491935	42	0	0
T6	31051	7	0	0
T7	26772	35	0	0
T15	30333	3	0	0
T16	14548	30	0	0
T17	1210756	57	0	0
T18	25874	3	0	0
T19	8524	2	0	0
T20	44539	0	0	0
T21	575887	0	0	0
T24	8891	22	0	0
T25	44097	31	0	0
T26	14828	36	0	0
T39	0	1	0	0
T157	0	29	0	0
T180	0	25	0	0
T181	0	30	0	0
T182	0	10	0	0
T183	0	5	0	0
T184	0	20	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	42550	0	0
T1	1236485	0	0	0
T2	2697098	0	0	0
T4	190449	0	0	0
T5	491935	0	0	0
T6	31051	8	0	0
T7	26772	42	0	0
T15	30333	0	0	0
T16	14548	48	0	0
T17	1210756	0	0	0
T18	25874	0	0	0
T19	8524	10	0	0
T20	44539	0	0	0
T21	575887	0	0	0
T24	8891	48	0	0
T25	44097	84	0	0
T26	14828	92	0	0
T39	0	8	0	0
T42	0	8	0	0
T130	0	6	0	0
T157	0	74	0	0
T158	0	55	0	0
T180	0	49	0	0
T181	0	46	0	0
T182	0	16	0	0
T183	0	8	0	0
T184	0	24	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T16
1	0	Unreachable
1	1	Covered	T6,T7,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	236949594	170	0	0
CgEnOn_A	236949594	170	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236949594	170	0	0
T2	119830	0	0	0
T16	592	3	0	0
T17	32859	0	0	0
T18	1285	0	0	0
T19	863	0	0	0
T20	4802	0	0	0
T21	37122	0	0	0
T24	923	4	0	0
T25	4232	5	0	0
T26	1514	6	0	0
T157	0	5	0	0
T180	0	5	0	0
T181	0	6	0	0
T182	0	2	0	0
T183	0	1	0	0
T184	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236949594	170	0	0
T2	119830	0	0	0
T16	592	3	0	0
T17	32859	0	0	0
T18	1285	0	0	0
T19	863	0	0	0
T20	4802	0	0	0
T21	37122	0	0	0
T24	923	4	0	0
T25	4232	5	0	0
T26	1514	6	0	0
T157	0	5	0	0
T180	0	5	0	0
T181	0	6	0	0
T182	0	2	0	0
T183	0	1	0	0
T184	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T16
1	0	Unreachable
1	1	Covered	T6,T7,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	118474156	170	0	0
CgEnOn_A	118474156	170	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118474156	170	0	0
T2	59915	0	0	0
T16	296	3	0	0
T17	16431	0	0	0
T18	640	0	0	0
T19	431	0	0	0
T20	2401	0	0	0
T21	18563	0	0	0
T24	461	4	0	0
T25	2116	5	0	0
T26	757	6	0	0
T157	0	5	0	0
T180	0	5	0	0
T181	0	6	0	0
T182	0	2	0	0
T183	0	1	0	0
T184	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118474156	170	0	0
T2	59915	0	0	0
T16	296	3	0	0
T17	16431	0	0	0
T18	640	0	0	0
T19	431	0	0	0
T20	2401	0	0	0
T21	18563	0	0	0
T24	461	4	0	0
T25	2116	5	0	0
T26	757	6	0	0
T157	0	5	0	0
T180	0	5	0	0
T181	0	6	0	0
T182	0	2	0	0
T183	0	1	0	0
T184	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T16
1	0	Unreachable
1	1	Covered	T6,T7,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	118474156	170	0	0
CgEnOn_A	118474156	170	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118474156	170	0	0
T2	59915	0	0	0
T16	296	3	0	0
T17	16431	0	0	0
T18	640	0	0	0
T19	431	0	0	0
T20	2401	0	0	0
T21	18563	0	0	0
T24	461	4	0	0
T25	2116	5	0	0
T26	757	6	0	0
T157	0	5	0	0
T180	0	5	0	0
T181	0	6	0	0
T182	0	2	0	0
T183	0	1	0	0
T184	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118474156	170	0	0
T2	59915	0	0	0
T16	296	3	0	0
T17	16431	0	0	0
T18	640	0	0	0
T19	431	0	0	0
T20	2401	0	0	0
T21	18563	0	0	0
T24	461	4	0	0
T25	2116	5	0	0
T26	757	6	0	0
T157	0	5	0	0
T180	0	5	0	0
T181	0	6	0	0
T182	0	2	0	0
T183	0	1	0	0
T184	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T16
1	0	Unreachable
1	1	Covered	T6,T7,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	118474156	170	0	0
CgEnOn_A	118474156	170	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118474156	170	0	0
T2	59915	0	0	0
T16	296	3	0	0
T17	16431	0	0	0
T18	640	0	0	0
T19	431	0	0	0
T20	2401	0	0	0
T21	18563	0	0	0
T24	461	4	0	0
T25	2116	5	0	0
T26	757	6	0	0
T157	0	5	0	0
T180	0	5	0	0
T181	0	6	0	0
T182	0	2	0	0
T183	0	1	0	0
T184	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118474156	170	0	0
T2	59915	0	0	0
T16	296	3	0	0
T17	16431	0	0	0
T18	640	0	0	0
T19	431	0	0	0
T20	2401	0	0	0
T21	18563	0	0	0
T24	461	4	0	0
T25	2116	5	0	0
T26	757	6	0	0
T157	0	5	0	0
T180	0	5	0	0
T181	0	6	0	0
T182	0	2	0	0
T183	0	1	0	0
T184	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T16
1	0	Unreachable
1	1	Covered	T6,T7,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	471662723	170	0	0
CgEnOn_A	471662723	164	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471662723	170	0	0
T2	239754	0	0	0
T16	1304	3	0	0
T17	116680	0	0	0
T18	2243	0	0	0
T19	1777	0	0	0
T20	9079	0	0	0
T21	134809	0	0	0
T24	1925	4	0	0
T25	8488	5	0	0
T26	3135	6	0	0
T157	0	5	0	0
T180	0	5	0	0
T181	0	6	0	0
T182	0	2	0	0
T183	0	1	0	0
T184	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471662723	164	0	0
T2	239754	0	0	0
T16	1304	3	0	0
T17	116680	0	0	0
T18	2243	0	0	0
T19	1777	0	0	0
T20	9079	0	0	0
T21	134809	0	0	0
T24	1925	4	0	0
T25	8488	5	0	0
T26	3135	6	0	0
T157	0	5	0	0
T180	0	5	0	0
T181	0	6	0	0
T182	0	2	0	0
T183	0	1	0	0
T184	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T16
1	0	Unreachable
1	1	Covered	T6,T7,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	502534067	160	0	0
CgEnOn_A	502534067	158	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502534067	160	0	0
T2	249751	0	0	0
T16	1371	3	0	0
T17	121545	0	0	0
T18	2336	0	0	0
T19	1851	0	0	0
T20	9458	0	0	0
T21	140430	0	0	0
T24	1873	2	0	0
T25	10175	6	0	0
T26	3221	6	0	0
T157	0	4	0	0
T180	0	6	0	0
T181	0	6	0	0
T182	0	2	0	0
T183	0	1	0	0
T184	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502534067	158	0	0
T2	249751	0	0	0
T16	1371	3	0	0
T17	121545	0	0	0
T18	2336	0	0	0
T19	1851	0	0	0
T20	9458	0	0	0
T21	140430	0	0	0
T24	1873	2	0	0
T25	10175	6	0	0
T26	3221	6	0	0
T157	0	4	0	0
T180	0	6	0	0
T181	0	6	0	0
T182	0	2	0	0
T183	0	1	0	0
T184	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T16
1	0	Unreachable
1	1	Covered	T6,T7,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	502534067	160	0	0
CgEnOn_A	502534067	158	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502534067	160	0	0
T2	249751	0	0	0
T16	1371	3	0	0
T17	121545	0	0	0
T18	2336	0	0	0
T19	1851	0	0	0
T20	9458	0	0	0
T21	140430	0	0	0
T24	1873	2	0	0
T25	10175	6	0	0
T26	3221	6	0	0
T157	0	4	0	0
T180	0	6	0	0
T181	0	6	0	0
T182	0	2	0	0
T183	0	1	0	0
T184	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502534067	158	0	0
T2	249751	0	0	0
T16	1371	3	0	0
T17	121545	0	0	0
T18	2336	0	0	0
T19	1851	0	0	0
T20	9458	0	0	0
T21	140430	0	0	0
T24	1873	2	0	0
T25	10175	6	0	0
T26	3221	6	0	0
T157	0	4	0	0
T180	0	6	0	0
T181	0	6	0	0
T182	0	2	0	0
T183	0	1	0	0
T184	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T16
1	0	Unreachable
1	1	Covered	T6,T7,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	241191408	147	0	0
CgEnOn_A	241191408	147	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241191408	147	0	0
T2	119882	0	0	0
T16	673	3	0	0
T17	58342	0	0	0
T18	1121	0	0	0
T19	889	0	0	0
T20	4539	0	0	0
T21	67407	0	0	0
T24	914	2	0	0
T25	4679	4	0	0
T26	1466	4	0	0
T157	0	5	0	0
T180	0	6	0	0
T181	0	4	0	0
T182	0	2	0	0
T183	0	1	0	0
T184	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241191408	147	0	0
T2	119882	0	0	0
T16	673	3	0	0
T17	58342	0	0	0
T18	1121	0	0	0
T19	889	0	0	0
T20	4539	0	0	0
T21	67407	0	0	0
T24	914	2	0	0
T25	4679	4	0	0
T26	1466	4	0	0
T157	0	5	0	0
T180	0	6	0	0
T181	0	4	0	0
T182	0	2	0	0
T183	0	1	0	0
T184	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T24,T25
1	0	Covered	T6,T7,T1
1	1	Covered	T6,T7,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	118474156	8164	0	0
CgEnOn_A	118474156	6007	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118474156	8164	0	0
T1	48162	1	0	0
T2	59915	1	0	0
T4	4960	6	0	0
T5	9936	14	0	0
T6	1198	2	0	0
T7	1022	12	0	0
T15	1217	1	0	0
T16	296	4	0	0
T17	16431	19	0	0
T18	640	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118474156	6007	0	0
T1	48162	0	0	0
T2	59915	0	0	0
T4	4960	0	0	0
T5	9936	0	0	0
T6	1198	1	0	0
T7	1022	11	0	0
T15	1217	0	0	0
T16	296	3	0	0
T17	16431	0	0	0
T18	640	0	0	0
T24	0	4	0	0
T25	0	5	0	0
T26	0	6	0	0
T39	0	1	0	0
T42	0	1	0	0
T157	0	5	0	0
T158	0	15	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T24,T25
1	0	Covered	T6,T7,T1
1	1	Covered	T6,T7,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	236949594	8225	0	0
CgEnOn_A	236949594	6068	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236949594	8225	0	0
T1	96324	1	0	0
T2	119830	1	0	0
T4	9919	6	0	0
T5	19873	14	0	0
T6	2397	2	0	0
T7	2045	12	0	0
T15	2434	1	0	0
T16	592	4	0	0
T17	32859	19	0	0
T18	1285	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236949594	6068	0	0
T1	96324	0	0	0
T2	119830	0	0	0
T4	9919	0	0	0
T5	19873	0	0	0
T6	2397	1	0	0
T7	2045	11	0	0
T15	2434	0	0	0
T16	592	3	0	0
T17	32859	0	0	0
T18	1285	0	0	0
T24	0	4	0	0
T25	0	5	0	0
T26	0	6	0	0
T39	0	1	0	0
T42	0	1	0	0
T157	0	5	0	0
T158	0	14	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T24,T25
1	0	Covered	T6,T7,T1
1	1	Covered	T6,T7,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	471662723	8240	0	0
CgEnOn_A	471662723	6077	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471662723	8240	0	0
T1	192700	1	0	0
T2	239754	1	0	0
T4	30982	6	0	0
T5	81550	14	0	0
T6	4846	2	0	0
T7	4182	11	0	0
T15	4708	1	0	0
T16	1304	4	0	0
T17	116680	19	0	0
T18	2243	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471662723	6077	0	0
T1	192700	0	0	0
T2	239754	0	0	0
T4	30982	0	0	0
T5	81550	0	0	0
T6	4846	1	0	0
T7	4182	10	0	0
T15	4708	0	0	0
T16	1304	3	0	0
T17	116680	0	0	0
T18	2243	0	0	0
T24	0	4	0	0
T25	0	5	0	0
T26	0	6	0	0
T39	0	1	0	0
T42	0	1	0	0
T157	0	5	0	0
T158	0	13	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T24,T25
1	0	Covered	T6,T7,T1
1	1	Covered	T6,T7,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	241191408	8183	0	0
CgEnOn_A	241191408	6019	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241191408	8183	0	0
T1	96355	1	0	0
T2	119882	1	0	0
T4	15492	6	0	0
T5	40776	14	0	0
T6	2422	2	0	0
T7	2091	11	0	0
T15	2354	1	0	0
T16	673	4	0	0
T17	58342	19	0	0
T18	1121	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241191408	6019	0	0
T1	96355	0	0	0
T2	119882	0	0	0
T4	15492	0	0	0
T5	40776	0	0	0
T6	2422	1	0	0
T7	2091	10	0	0
T15	2354	0	0	0
T16	673	3	0	0
T17	58342	0	0	0
T18	1121	0	0	0
T24	0	2	0	0
T25	0	4	0	0
T26	0	4	0	0
T39	0	1	0	0
T42	0	1	0	0
T157	0	5	0	0
T158	0	13	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T16
1	0	Covered	T6,T19,T39
1	1	Covered	T6,T7,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	502534067	4260	0	0
CgEnOn_A	502534067	4258	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502534067	4260	0	0
T1	200736	0	0	0
T2	249751	0	0	0
T4	32274	0	0	0
T5	84950	0	0	0
T6	5047	1	0	0
T7	4358	0	0	0
T15	4905	0	0	0
T16	1371	3	0	0
T17	121545	0	0	0
T18	2336	0	0	0
T19	0	2	0	0
T24	0	2	0	0
T25	0	6	0	0
T26	0	6	0	0
T39	0	1	0	0
T42	0	1	0	0
T130	0	1	0	0
T157	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502534067	4258	0	0
T1	200736	0	0	0
T2	249751	0	0	0
T4	32274	0	0	0
T5	84950	0	0	0
T6	5047	1	0	0
T7	4358	0	0	0
T15	4905	0	0	0
T16	1371	3	0	0
T17	121545	0	0	0
T18	2336	0	0	0
T19	0	2	0	0
T24	0	2	0	0
T25	0	6	0	0
T26	0	6	0	0
T39	0	1	0	0
T42	0	1	0	0
T130	0	1	0	0
T157	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T16
1	0	Covered	T6,T19,T39
1	1	Covered	T6,T7,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	502534067	4315	0	0
CgEnOn_A	502534067	4313	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502534067	4315	0	0
T1	200736	0	0	0
T2	249751	0	0	0
T4	32274	0	0	0
T5	84950	0	0	0
T6	5047	1	0	0
T7	4358	0	0	0
T15	4905	0	0	0
T16	1371	3	0	0
T17	121545	0	0	0
T18	2336	0	0	0
T19	0	2	0	0
T24	0	2	0	0
T25	0	6	0	0
T26	0	6	0	0
T39	0	1	0	0
T42	0	1	0	0
T157	0	4	0	0
T180	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502534067	4313	0	0
T1	200736	0	0	0
T2	249751	0	0	0
T4	32274	0	0	0
T5	84950	0	0	0
T6	5047	1	0	0
T7	4358	0	0	0
T15	4905	0	0	0
T16	1371	3	0	0
T17	121545	0	0	0
T18	2336	0	0	0
T19	0	2	0	0
T24	0	2	0	0
T25	0	6	0	0
T26	0	6	0	0
T39	0	1	0	0
T42	0	1	0	0
T157	0	4	0	0
T180	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T16
1	0	Covered	T6,T19,T39
1	1	Covered	T6,T7,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	502534067	4275	0	0
CgEnOn_A	502534067	4273	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502534067	4275	0	0
T1	200736	0	0	0
T2	249751	0	0	0
T4	32274	0	0	0
T5	84950	0	0	0
T6	5047	1	0	0
T7	4358	0	0	0
T15	4905	0	0	0
T16	1371	3	0	0
T17	121545	0	0	0
T18	2336	0	0	0
T19	0	3	0	0
T24	0	2	0	0
T25	0	6	0	0
T26	0	6	0	0
T39	0	1	0	0
T42	0	1	0	0
T130	0	4	0	0
T157	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502534067	4273	0	0
T1	200736	0	0	0
T2	249751	0	0	0
T4	32274	0	0	0
T5	84950	0	0	0
T6	5047	1	0	0
T7	4358	0	0	0
T15	4905	0	0	0
T16	1371	3	0	0
T17	121545	0	0	0
T18	2336	0	0	0
T19	0	3	0	0
T24	0	2	0	0
T25	0	6	0	0
T26	0	6	0	0
T39	0	1	0	0
T42	0	1	0	0
T130	0	4	0	0
T157	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T16
1	0	Covered	T6,T19,T39
1	1	Covered	T6,T7,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	502534067	4230	0	0
CgEnOn_A	502534067	4228	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502534067	4230	0	0
T1	200736	0	0	0
T2	249751	0	0	0
T4	32274	0	0	0
T5	84950	0	0	0
T6	5047	1	0	0
T7	4358	0	0	0
T15	4905	0	0	0
T16	1371	3	0	0
T17	121545	0	0	0
T18	2336	0	0	0
T19	0	3	0	0
T24	0	2	0	0
T25	0	6	0	0
T26	0	6	0	0
T39	0	1	0	0
T42	0	1	0	0
T130	0	1	0	0
T157	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502534067	4228	0	0
T1	200736	0	0	0
T2	249751	0	0	0
T4	32274	0	0	0
T5	84950	0	0	0
T6	5047	1	0	0
T7	4358	0	0	0
T15	4905	0	0	0
T16	1371	3	0	0
T17	121545	0	0	0
T18	2336	0	0	0
T19	0	3	0	0
T24	0	2	0	0
T25	0	6	0	0
T26	0	6	0	0
T39	0	1	0	0
T42	0	1	0	0
T130	0	1	0	0
T157	0	4	0	0