Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_trans_cg_wrap::trans_cg

Group : clkmgr_env_pkg::clkmgr_trans_cg_wrap::trans_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
TransAes	100.00	1	100	1	64	64
TransHmac	100.00	1	100	1	64	64
TransKmac	100.00	1	100	1	64	64
TransOtbn	100.00	1	100	1	64	64

---

Group Instance : TransAes

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance TransAes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	10	0	10	100.00

Variables for Group Instance TransAes

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_hint_cp	2	0	2	100.00	100	1	1	2
idle_cp	2	0	2	100.00	100	1	1	2
ip_clk_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance TransAes

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
trans_cross	10	0	10	100.00	100	1	1	0

---

Group Instance : TransHmac

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance TransHmac

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	10	0	10	100.00

Variables for Group Instance TransHmac

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_hint_cp	2	0	2	100.00	100	1	1	2
idle_cp	2	0	2	100.00	100	1	1	2
ip_clk_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance TransHmac

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
trans_cross	10	0	10	100.00	100	1	1	0

---

Group Instance : TransKmac

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance TransKmac

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	10	0	10	100.00

Variables for Group Instance TransKmac

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_hint_cp	2	0	2	100.00	100	1	1	2
idle_cp	2	0	2	100.00	100	1	1	2
ip_clk_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance TransKmac

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
trans_cross	10	0	10	100.00	100	1	1	0

---

Group Instance : TransOtbn

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance TransOtbn

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	10	0	10	100.00

Variables for Group Instance TransOtbn

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_hint_cp	2	0	2	100.00	100	1	1	2
idle_cp	2	0	2	100.00	100	1	1	2
ip_clk_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance TransOtbn

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
trans_cross	10	0	10	100.00	100	1	1	0

Summary for Variable csr_hint_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_hint_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1313934

1

T4

2

T5

2

T1

2520

auto[1]

520703120

1

T4

4617

T5

5492

T1

356550

---

Summary for Variable idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for idle_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

437435712

1

T4

246

T5

5493

T1

228145

auto[1]

84581342

1

T4

4373

T5

1

T1

128657

---

Summary for Variable ip_clk_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for ip_clk_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9152

1

T4

2

T5

2

T1

12

auto[1]

522007902

1

T4

4617

T5

5492

T1

356801

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

324902181

1

T4

4434

T5

194

T1

127231

auto[1]

197114873

1

T4

185

T5

5300

T1

229571

---

Summary for Cross trans_cross

Samples crossed: csr_hint_cp ip_clk_en_cp scanmode_cp idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	10	0	10	100.00
Automatically Generated Cross Bins	10	0	10	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for trans_cross

Bins

csr_hint_cp

ip_clk_en_cp

scanmode_cp

idle_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[1]

2714

1

T1

4

T9

4

T11

2

auto[0]

auto[0]

auto[1]

auto[1]

22

1

T1

2

T11

2

T74

2

auto[0]

auto[1]

auto[0]

auto[0]

434152

1

T1

961

T18

95

T2

600

auto[0]

auto[1]

auto[0]

auto[1]

412619

1

T1

254

T18

27

T9

1834

auto[0]

auto[1]

auto[1]

auto[0]

382587

1

T1

1123

T18

107

T26

234

auto[0]

auto[1]

auto[1]

auto[1]

77526

1

T1

170

T18

22

T26

85

auto[1]

auto[1]

auto[0]

auto[0]

259133489

1

T4

61

T5

192

T1

795958

auto[1]

auto[1]

auto[0]

auto[1]

64914339

1

T4

4373

T1

475133

T16

4655

auto[1]

auto[1]

auto[1]

auto[0]

177480089

1

T4

183

T5

5299

T1

148340

auto[1]

auto[1]

auto[1]

auto[1]

19173101

1

T5

1

T1

811009

T16

258

User Defined Cross Bins for trans_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore_idle_off	0	Excluded
ignore_enable_off	0	Excluded

Summary for Variable csr_hint_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_hint_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1274558

1

T4

2

T5

415

T1

1875

auto[1]

520742496

1

T4

4617

T5

5079

T1

356614

---

Summary for Variable idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for idle_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

454734757

1

T4

352

T5

5233

T1

308985

auto[1]

67282297

1

T4

4267

T5

261

T1

478167

---

Summary for Variable ip_clk_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for ip_clk_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9152

1

T4

2

T5

2

T1

12

auto[1]

522007902

1

T4

4617

T5

5492

T1

356801

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

324902181

1

T4

4434

T5

194

T1

127231

auto[1]

197114873

1

T4

185

T5

5300

T1

229571

---

Summary for Cross trans_cross

Samples crossed: csr_hint_cp ip_clk_en_cp scanmode_cp idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	10	0	10	100.00
Automatically Generated Cross Bins	10	0	10	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for trans_cross

Bins

csr_hint_cp

ip_clk_en_cp

scanmode_cp

idle_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[1]

2692

1

T1

4

T9

2

T12

2

auto[0]

auto[0]

auto[1]

auto[1]

32

1

T9

2

T11

2

T13

2

auto[0]

auto[1]

auto[0]

auto[0]

400000

1

T1

681

T18

204

T2

450

auto[0]

auto[1]

auto[0]

auto[1]

437104

1

T1

151

T18

56

T9

1517

auto[0]

auto[1]

auto[1]

auto[0]

352338

1

T5

240

T1

842

T18

249

auto[0]

auto[1]

auto[1]

auto[1]

78066

1

T5

173

T1

189

T26

57

auto[1]

auto[1]

auto[0]

auto[0]

279570518

1

T4

217

T5

192

T1

795699

auto[1]

auto[1]

auto[0]

auto[1]

44486977

1

T4

4217

T1

475775

T16

5067

auto[1]

auto[1]

auto[1]

auto[0]

174406485

1

T4

133

T5

4799

T1

229262

auto[1]

auto[1]

auto[1]

auto[1]

22276414

1

T4

50

T5

88

T1

2048

User Defined Cross Bins for trans_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore_idle_off	0	Excluded
ignore_enable_off	0	Excluded

Summary for Variable csr_hint_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_hint_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1216196

1

T4

2

T5

2

T1

1740

auto[1]

520800858

1

T4

4617

T5

5492

T1

356628

---

Summary for Variable idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for idle_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

432635980

1

T4

252

T5

5233

T1

322651

auto[1]

89381074

1

T4

4367

T5

261

T1

341508

---

Summary for Variable ip_clk_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for ip_clk_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9152

1

T4

2

T5

2

T1

12

auto[1]

522007902

1

T4

4617

T5

5492

T1

356801

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

324902181

1

T4

4434

T5

194

T1

127231

auto[1]

197114873

1

T4

185

T5

5300

T1

229571

---

Summary for Cross trans_cross

Samples crossed: csr_hint_cp ip_clk_en_cp scanmode_cp idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	10	0	10	100.00
Automatically Generated Cross Bins	10	0	10	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for trans_cross

Bins

csr_hint_cp

ip_clk_en_cp

scanmode_cp

idle_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[1]

2706

1

T1

2

T9

2

T11

2

auto[0]

auto[0]

auto[1]

auto[1]

24

1

T1

2

T9

2

T11

2

auto[0]

auto[1]

auto[0]

auto[0]

354348

1

T1

656

T18

168

T2

300

auto[0]

auto[1]

auto[0]

auto[1]

435933

1

T1

149

T18

86

T26

227

auto[0]

auto[1]

auto[1]

auto[0]

335289

1

T1

774

T18

393

T26

324

auto[0]

auto[1]

auto[1]

auto[1]

83576

1

T1

149

T18

127

T26

288

auto[1]

auto[1]

auto[0]

auto[0]

251638985

1

T4

117

T5

192

T1

126756

auto[1]

auto[1]

auto[0]

auto[1]

72465333

1

T4

4317

T1

3933

T16

1075

auto[1]

auto[1]

auto[1]

auto[0]

180301621

1

T4

133

T5

5039

T1

195751

auto[1]

auto[1]

auto[1]

auto[1]

16392817

1

T4

50

T5

261

T1

337273

User Defined Cross Bins for trans_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore_idle_off	0	Excluded
ignore_enable_off	0	Excluded

Summary for Variable csr_hint_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_hint_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1136141

1

T4

2

T5

2

T1

1786

auto[1]

520880913

1

T4

4617

T5

5492

T1

356623

---

Summary for Variable idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for idle_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

468032218

1

T4

196

T5

5232

T1

356124

auto[1]

53984836

1

T4

4423

T5

262

T1

6776

---

Summary for Variable ip_clk_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for ip_clk_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9152

1

T4

2

T5

2

T1

12

auto[1]

522007902

1

T4

4617

T5

5492

T1

356801

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

324902181

1

T4

4434

T5

194

T1

127231

auto[1]

197114873

1

T4

185

T5

5300

T1

229571

---

Summary for Cross trans_cross

Samples crossed: csr_hint_cp ip_clk_en_cp scanmode_cp idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	10	0	10	100.00
Automatically Generated Cross Bins	10	0	10	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for trans_cross

Bins

csr_hint_cp

ip_clk_en_cp

scanmode_cp

idle_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[1]

2694

1

T9

2

T12

6

T13

2

auto[0]

auto[0]

auto[1]

auto[1]

32

1

T9

2

T13

2

T74

2

auto[0]

auto[1]

auto[0]

auto[0]

318829

1

T1

727

T18

115

T2

150

auto[0]

auto[1]

auto[0]

auto[1]

438660

1

T1

42

T18

85

T26

224

auto[0]

auto[1]

auto[1]

auto[0]

292072

1

T1

812

T18

277

T26

399

auto[0]

auto[1]

auto[1]

auto[1]

79530

1

T1

193

T18

102

T26

57

auto[1]

auto[1]

auto[0]

auto[0]

284911361

1

T4

61

T5

192

T1

126719

auto[1]

auto[1]

auto[0]

auto[1]

39225749

1

T4

4373

T1

4343

T16

4838

auto[1]

auto[1]

auto[1]

auto[0]

182504739

1

T4

133

T5

5038

T1

229250

auto[1]

auto[1]

auto[1]

auto[1]

14236962

1

T4

50

T5

262

T1

2198

User Defined Cross Bins for trans_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore_idle_off	0	Excluded
ignore_enable_off	0	Excluded