Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T5,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T38,T39,T40
1	1	Covered	T4,T5,T1

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1112514300	13101	0	0
GateOpen_A	1112514300	19956	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1112514300	13101	0	0
T1	1488675	135	0	0
T2	1226525	30	0	0
T4	10271	22	0	0
T5	12103	0	0	0
T9	0	318	0	0
T11	0	397	0	0
T12	0	197	0	0
T16	15878	0	0	0
T17	3906	0	0	0
T18	7829	0	0	0
T19	3975	0	0	0
T20	8019	0	0	0
T21	4376	0	0	0
T22	0	8	0	0
T28	0	32	0	0
T38	0	3	0	0
T39	0	14	0	0
T121	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1112514300	19956	0	0
T1	1488675	147	0	0
T2	1226525	46	0	0
T4	10271	22	0	0
T5	12103	4	0	0
T16	15878	4	0	0
T17	3906	4	0	0
T18	7829	4	0	0
T19	3975	0	0	0
T20	8019	4	0	0
T21	4376	4	0	0
T22	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T5,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T38,T39,T40
1	1	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	122975568	3109	0	0
GateOpen_A	122975568	4821	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122975568	3109	0	0
T1	823867	28	0	0
T2	131709	6	0	0
T4	1133	6	0	0
T5	1330	0	0	0
T9	0	76	0	0
T11	0	96	0	0
T12	0	98	0	0
T16	1910	0	0	0
T17	432	0	0	0
T18	848	0	0	0
T19	440	0	0	0
T20	884	0	0	0
T21	498	0	0	0
T22	0	2	0	0
T28	0	7	0	0
T38	0	1	0	0
T39	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122975568	4821	0	0
T1	823867	31	0	0
T2	131709	10	0	0
T4	1133	6	0	0
T5	1330	1	0	0
T16	1910	1	0	0
T17	432	1	0	0
T18	848	1	0	0
T19	440	0	0	0
T20	884	1	0	0
T21	498	1	0	0
T22	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T5,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T38,T39,T40
1	1	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	245952037	3352	0	0
GateOpen_A	245952037	5064	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	245952037	3352	0	0
T1	164774	33	0	0
T2	263417	8	0	0
T4	2265	5	0	0
T5	2659	0	0	0
T9	0	81	0	0
T11	0	104	0	0
T16	3820	0	0	0
T17	866	0	0	0
T18	1695	0	0	0
T19	881	0	0	0
T20	1768	0	0	0
T21	998	0	0	0
T22	0	2	0	0
T28	0	8	0	0
T38	0	1	0	0
T39	0	4	0	0
T121	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	245952037	5064	0	0
T1	164774	36	0	0
T2	263417	12	0	0
T4	2265	5	0	0
T5	2659	1	0	0
T16	3820	1	0	0
T17	866	1	0	0
T18	1695	1	0	0
T19	881	0	0	0
T20	1768	1	0	0
T21	998	1	0	0
T22	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T5,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T38,T39,T40
1	1	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	492121301	3321	0	0
GateOpen_A	492121301	5036	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492121301	3321	0	0
T1	329895	38	0	0
T2	527377	9	0	0
T4	4582	6	0	0
T5	5409	0	0	0
T9	0	81	0	0
T11	0	98	0	0
T16	6765	0	0	0
T17	1739	0	0	0
T18	3524	0	0	0
T19	1769	0	0	0
T20	3578	0	0	0
T21	1920	0	0	0
T22	0	2	0	0
T28	0	8	0	0
T38	0	1	0	0
T39	0	4	0	0
T121	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492121301	5036	0	0
T1	329895	41	0	0
T2	527377	13	0	0
T4	4582	6	0	0
T5	5409	1	0	0
T16	6765	1	0	0
T17	1739	1	0	0
T18	3524	1	0	0
T19	1769	0	0	0
T20	3578	1	0	0
T21	1920	1	0	0
T22	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T5,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T39,T40,T41
1	1	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	251465394	3319	0	0
GateOpen_A	251465394	5035	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	251465394	3319	0	0
T1	170139	36	0	0
T2	304022	7	0	0
T4	2291	5	0	0
T5	2705	0	0	0
T9	0	80	0	0
T11	0	99	0	0
T12	0	99	0	0
T16	3383	0	0	0
T17	869	0	0	0
T18	1762	0	0	0
T19	885	0	0	0
T20	1789	0	0	0
T21	960	0	0	0
T22	0	2	0	0
T28	0	9	0	0
T39	0	2	0	0
T121	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	251465394	5035	0	0
T1	170139	39	0	0
T2	304022	11	0	0
T4	2291	5	0	0
T5	2705	1	0	0
T16	3383	1	0	0
T17	869	1	0	0
T18	1762	1	0	0
T19	885	0	0	0
T20	1789	1	0	0
T21	960	1	0	0
T22	0	2	0	0