Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.ack_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.ack_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.ack_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.ack_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_out.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_out.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_main_meas.u_meas.ack_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.ack_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_main_meas.u_meas.ack_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.ack_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_out.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_out.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_ref_meas_en_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_ref_meas_en_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_ref_meas_en_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_ref_meas_en_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.ack_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.ack_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.ack_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.ack_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_out.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_out.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_infra.gen_flops.u_prim_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_infra.gen_flops.u_prim_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_infra.gen_flops.u_prim_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_infra.gen_flops.u_prim_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_infra.gen_flops.u_prim_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_infra.gen_flops.u_prim_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_infra.gen_flops.u_prim_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_infra.gen_flops.u_prim_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_infra.gen_flops.u_prim_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_infra.gen_flops.u_prim_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_secure.gen_flops.u_prim_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_secure.gen_flops.u_prim_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_secure.gen_flops.u_prim_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_secure.gen_flops.u_prim_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_timers.gen_flops.u_prim_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_timers.gen_flops.u_prim_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_sw_en_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clk_io_div4_peri_sw_en_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_sw_en_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clk_io_div4_peri_sw_en_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_peri.gen_flops.u_prim_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_peri.gen_flops.u_prim_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_sw_en_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clk_io_div2_peri_sw_en_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_sw_en_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clk_io_div2_peri_sw_en_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_peri.gen_flops.u_prim_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_peri.gen_flops.u_prim_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_clk_io_peri_sw_en_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clk_io_peri_sw_en_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_clk_io_peri_sw_en_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clk_io_peri_sw_en_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_peri.gen_flops.u_prim_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_peri.gen_flops.u_prim_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_clk_usb_peri_sw_en_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clk_usb_peri_sw_en_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_clk_usb_peri_sw_en_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clk_usb_peri_sw_en_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_peri.gen_flops.u_prim_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_peri.gen_flops.u_prim_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_hint_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_hint_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_hint_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_hint_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_err_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_err_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_err_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_err_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_en_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_en_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_en_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_en_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_hint_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_hint_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_hint_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_hint_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_err_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_err_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_err_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_err_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_en_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_en_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_en_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_en_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_hint_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_hint_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_hint_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_hint_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_err_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_err_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_err_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_err_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_en_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_en_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_en_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_en_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_hint_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_hint_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_hint_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_hint_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_err_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_err_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_err_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_err_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_en_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_en_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_en_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_en_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |