Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	861237600	72907	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	861237600	72907	0	0
T1	1820260	1035	0	0
T2	602420	124	0	0
T3	425210	195	0	0
T9	0	1099	0	0
T10	0	92	0	0
T11	0	1230	0	0
T12	0	1960	0	0
T13	0	684	0	0
T14	0	945	0	0
T15	0	250	0	0
T16	8450	0	0	0
T17	9050	0	0	0
T18	17440	0	0	0
T19	8840	0	0	0
T20	4655	0	0	0
T21	9595	0	0	0
T22	8045	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	172247520	10689	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172247520	10689	0	0
T1	364052	132	0	0
T2	120484	20	0	0
T3	85042	28	0	0
T9	0	176	0	0
T10	0	15	0	0
T11	0	223	0	0
T12	0	316	0	0
T13	0	108	0	0
T14	0	149	0	0
T15	0	36	0	0
T16	1690	0	0	0
T17	1810	0	0	0
T18	3488	0	0	0
T19	1768	0	0	0
T20	931	0	0	0
T21	1919	0	0	0
T22	1609	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	172247520	10464	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172247520	10464	0	0
T1	364052	149	0	0
T2	120484	20	0	0
T3	85042	27	0	0
T9	0	174	0	0
T10	0	14	0	0
T11	0	223	0	0
T12	0	311	0	0
T13	0	106	0	0
T14	0	148	0	0
T15	0	36	0	0
T16	1690	0	0	0
T17	1810	0	0	0
T18	3488	0	0	0
T19	1768	0	0	0
T20	931	0	0	0
T21	1919	0	0	0
T22	1609	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	172247520	14652	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172247520	14652	0	0
T1	364052	206	0	0
T2	120484	25	0	0
T3	85042	44	0	0
T9	0	222	0	0
T10	0	18	0	0
T11	0	240	0	0
T12	0	399	0	0
T13	0	134	0	0
T14	0	191	0	0
T15	0	49	0	0
T16	1690	0	0	0
T17	1810	0	0	0
T18	3488	0	0	0
T19	1768	0	0	0
T20	931	0	0	0
T21	1919	0	0	0
T22	1609	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	172247520	14652	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172247520	14652	0	0
T1	364052	204	0	0
T2	120484	25	0	0
T3	85042	38	0	0
T9	0	222	0	0
T10	0	18	0	0
T11	0	240	0	0
T12	0	397	0	0
T13	0	137	0	0
T14	0	191	0	0
T15	0	50	0	0
T16	1690	0	0	0
T17	1810	0	0	0
T18	3488	0	0	0
T19	1768	0	0	0
T20	931	0	0	0
T21	1919	0	0	0
T22	1609	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	172247520	22450	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172247520	22450	0	0
T1	364052	344	0	0
T2	120484	34	0	0
T3	85042	58	0	0
T9	0	305	0	0
T10	0	27	0	0
T11	0	304	0	0
T12	0	537	0	0
T13	0	199	0	0
T14	0	266	0	0
T15	0	79	0	0
T16	1690	0	0	0
T17	1810	0	0	0
T18	3488	0	0	0
T19	1768	0	0	0
T20	931	0	0	0
T21	1919	0	0	0
T22	1609	0	0	0