Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=1,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=6,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Module :
prim_mubi4_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T1 |
1 | Covered | T4,T5,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T1 |
1 | Covered | T4,T5,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T1 |
1 | Covered | T4,T5,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T1 |
1 | Covered | T4,T5,T1 |
Branch Coverage for Module :
prim_mubi4_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Module :
prim_mubi4_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22540 |
22540 |
0 |
0 |
T1 |
28 |
28 |
0 |
0 |
T2 |
28 |
28 |
0 |
0 |
T4 |
28 |
28 |
0 |
0 |
T5 |
28 |
28 |
0 |
0 |
T16 |
28 |
28 |
0 |
0 |
T17 |
28 |
28 |
0 |
0 |
T18 |
28 |
28 |
0 |
0 |
T19 |
28 |
28 |
0 |
0 |
T20 |
28 |
28 |
0 |
0 |
T21 |
28 |
28 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
10132366 |
10116439 |
0 |
0 |
T2 |
9410988 |
9395067 |
0 |
0 |
T4 |
65828 |
64064 |
0 |
0 |
T5 |
80839 |
79031 |
0 |
0 |
T16 |
109725 |
108392 |
0 |
0 |
T17 |
47271 |
42200 |
0 |
0 |
T18 |
93220 |
87207 |
0 |
0 |
T19 |
47080 |
43348 |
0 |
0 |
T20 |
58162 |
56104 |
0 |
0 |
T21 |
51151 |
45162 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1033485120 |
1017622542 |
0 |
14490 |
T1 |
2184312 |
2180400 |
0 |
18 |
T2 |
722904 |
721440 |
0 |
18 |
T4 |
3438 |
3312 |
0 |
18 |
T5 |
5406 |
5256 |
0 |
18 |
T16 |
10140 |
9984 |
0 |
18 |
T17 |
10860 |
9570 |
0 |
18 |
T18 |
20928 |
19458 |
0 |
18 |
T19 |
10608 |
9702 |
0 |
18 |
T20 |
5586 |
5334 |
0 |
18 |
T21 |
11514 |
10026 |
0 |
18 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
16905 |
T1 |
2487807 |
2483270 |
0 |
21 |
T2 |
3421816 |
3414944 |
0 |
21 |
T4 |
24819 |
23998 |
0 |
21 |
T5 |
29751 |
28988 |
0 |
21 |
T16 |
38333 |
37780 |
0 |
21 |
T17 |
12598 |
11101 |
0 |
21 |
T18 |
25183 |
23414 |
0 |
21 |
T19 |
12676 |
11591 |
0 |
21 |
T20 |
20343 |
19480 |
0 |
21 |
T21 |
13753 |
11977 |
0 |
21 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
197819 |
0 |
0 |
T1 |
2487807 |
1368 |
0 |
0 |
T2 |
3421816 |
94 |
0 |
0 |
T3 |
340159 |
0 |
0 |
0 |
T4 |
19092 |
28 |
0 |
0 |
T5 |
22540 |
15 |
0 |
0 |
T9 |
0 |
932 |
0 |
0 |
T16 |
38333 |
169 |
0 |
0 |
T17 |
12598 |
128 |
0 |
0 |
T18 |
25183 |
140 |
0 |
0 |
T19 |
12676 |
95 |
0 |
0 |
T20 |
20343 |
18 |
0 |
0 |
T21 |
13753 |
138 |
0 |
0 |
T22 |
4778 |
0 |
0 |
0 |
T27 |
0 |
13 |
0 |
0 |
T29 |
0 |
76 |
0 |
0 |
T30 |
0 |
96 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
5460247 |
5452744 |
0 |
0 |
T2 |
5266268 |
5258449 |
0 |
0 |
T4 |
37571 |
36715 |
0 |
0 |
T5 |
45682 |
44748 |
0 |
0 |
T16 |
61252 |
60589 |
0 |
0 |
T17 |
23813 |
21490 |
0 |
0 |
T18 |
47109 |
44296 |
0 |
0 |
T19 |
23796 |
22016 |
0 |
0 |
T20 |
32233 |
31251 |
0 |
0 |
T21 |
25884 |
23120 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T1 |
1 | Covered | T1,T16,T17 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T1 |
1 | Covered | T1,T16,T17 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T1 |
1 | Covered | T1,T16,T17 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T1 |
1 | Covered | T1,T16,T17 |
Branch Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T16,T17 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T16,T17 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T16,T17 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T16,T17 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_io_step_down_req_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
492120848 |
487835614 |
0 |
0 |
T1 |
329895 |
329271 |
0 |
0 |
T2 |
527376 |
526158 |
0 |
0 |
T4 |
4581 |
4433 |
0 |
0 |
T5 |
5409 |
5275 |
0 |
0 |
T16 |
6765 |
6671 |
0 |
0 |
T17 |
1738 |
1534 |
0 |
0 |
T18 |
3523 |
3279 |
0 |
0 |
T19 |
1768 |
1620 |
0 |
0 |
T20 |
3577 |
3429 |
0 |
0 |
T21 |
1919 |
1674 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
492120848 |
487828483 |
0 |
2415 |
T1 |
329895 |
329270 |
0 |
3 |
T2 |
527376 |
526140 |
0 |
3 |
T4 |
4581 |
4430 |
0 |
3 |
T5 |
5409 |
5272 |
0 |
3 |
T16 |
6765 |
6668 |
0 |
3 |
T17 |
1738 |
1531 |
0 |
3 |
T18 |
3523 |
3276 |
0 |
3 |
T19 |
1768 |
1617 |
0 |
3 |
T20 |
3577 |
3426 |
0 |
3 |
T21 |
1919 |
1671 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
492120848 |
28054 |
0 |
0 |
T1 |
329895 |
122 |
0 |
0 |
T2 |
527376 |
0 |
0 |
0 |
T3 |
170075 |
0 |
0 |
0 |
T9 |
0 |
394 |
0 |
0 |
T16 |
6765 |
63 |
0 |
0 |
T17 |
1738 |
34 |
0 |
0 |
T18 |
3523 |
0 |
0 |
0 |
T19 |
1768 |
26 |
0 |
0 |
T20 |
3577 |
4 |
0 |
0 |
T21 |
1919 |
49 |
0 |
0 |
T22 |
1560 |
0 |
0 |
0 |
T27 |
0 |
4 |
0 |
0 |
T29 |
0 |
19 |
0 |
0 |
T30 |
0 |
41 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172247520 |
169611074 |
0 |
0 |
T1 |
364052 |
363402 |
0 |
0 |
T2 |
120484 |
120258 |
0 |
0 |
T4 |
573 |
555 |
0 |
0 |
T5 |
901 |
879 |
0 |
0 |
T16 |
1690 |
1667 |
0 |
0 |
T17 |
1810 |
1598 |
0 |
0 |
T18 |
3488 |
3246 |
0 |
0 |
T19 |
1768 |
1620 |
0 |
0 |
T20 |
931 |
892 |
0 |
0 |
T21 |
1919 |
1674 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172247520 |
169611074 |
0 |
0 |
T1 |
364052 |
363402 |
0 |
0 |
T2 |
120484 |
120258 |
0 |
0 |
T4 |
573 |
555 |
0 |
0 |
T5 |
901 |
879 |
0 |
0 |
T16 |
1690 |
1667 |
0 |
0 |
T17 |
1810 |
1598 |
0 |
0 |
T18 |
3488 |
3246 |
0 |
0 |
T19 |
1768 |
1620 |
0 |
0 |
T20 |
931 |
892 |
0 |
0 |
T21 |
1919 |
1674 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172247520 |
169611074 |
0 |
0 |
T1 |
364052 |
363402 |
0 |
0 |
T2 |
120484 |
120258 |
0 |
0 |
T4 |
573 |
555 |
0 |
0 |
T5 |
901 |
879 |
0 |
0 |
T16 |
1690 |
1667 |
0 |
0 |
T17 |
1810 |
1598 |
0 |
0 |
T18 |
3488 |
3246 |
0 |
0 |
T19 |
1768 |
1620 |
0 |
0 |
T20 |
931 |
892 |
0 |
0 |
T21 |
1919 |
1674 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172247520 |
169611074 |
0 |
0 |
T1 |
364052 |
363402 |
0 |
0 |
T2 |
120484 |
120258 |
0 |
0 |
T4 |
573 |
555 |
0 |
0 |
T5 |
901 |
879 |
0 |
0 |
T16 |
1690 |
1667 |
0 |
0 |
T17 |
1810 |
1598 |
0 |
0 |
T18 |
3488 |
3246 |
0 |
0 |
T19 |
1768 |
1620 |
0 |
0 |
T20 |
931 |
892 |
0 |
0 |
T21 |
1919 |
1674 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T1 |
1 | Covered | T1,T16,T17 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T1 |
1 | Covered | T1,T16,T17 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T1 |
1 | Covered | T1,T16,T17 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T1 |
1 | Covered | T1,T16,T17 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T16,T17 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T16,T17 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T16,T17 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T16,T17 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172247520 |
169611074 |
0 |
0 |
T1 |
364052 |
363402 |
0 |
0 |
T2 |
120484 |
120258 |
0 |
0 |
T4 |
573 |
555 |
0 |
0 |
T5 |
901 |
879 |
0 |
0 |
T16 |
1690 |
1667 |
0 |
0 |
T17 |
1810 |
1598 |
0 |
0 |
T18 |
3488 |
3246 |
0 |
0 |
T19 |
1768 |
1620 |
0 |
0 |
T20 |
931 |
892 |
0 |
0 |
T21 |
1919 |
1674 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172247520 |
169603757 |
0 |
2415 |
T1 |
364052 |
363400 |
0 |
3 |
T2 |
120484 |
120240 |
0 |
3 |
T4 |
573 |
552 |
0 |
3 |
T5 |
901 |
876 |
0 |
3 |
T16 |
1690 |
1664 |
0 |
3 |
T17 |
1810 |
1595 |
0 |
3 |
T18 |
3488 |
3243 |
0 |
3 |
T19 |
1768 |
1617 |
0 |
3 |
T20 |
931 |
889 |
0 |
3 |
T21 |
1919 |
1671 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172247520 |
17532 |
0 |
0 |
T1 |
364052 |
85 |
0 |
0 |
T2 |
120484 |
0 |
0 |
0 |
T3 |
85042 |
0 |
0 |
0 |
T9 |
0 |
243 |
0 |
0 |
T16 |
1690 |
30 |
0 |
0 |
T17 |
1810 |
4 |
0 |
0 |
T18 |
3488 |
0 |
0 |
0 |
T19 |
1768 |
12 |
0 |
0 |
T20 |
931 |
4 |
0 |
0 |
T21 |
1919 |
22 |
0 |
0 |
T22 |
1609 |
0 |
0 |
0 |
T27 |
0 |
5 |
0 |
0 |
T29 |
0 |
30 |
0 |
0 |
T30 |
0 |
28 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T1 |
1 | Covered | T1,T16,T17 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T1 |
1 | Covered | T1,T16,T17 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T1 |
1 | Covered | T1,T16,T17 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T1 |
1 | Covered | T1,T16,T17 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T16,T17 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T16,T17 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T16,T17 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T16,T17 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172247520 |
169611074 |
0 |
0 |
T1 |
364052 |
363402 |
0 |
0 |
T2 |
120484 |
120258 |
0 |
0 |
T4 |
573 |
555 |
0 |
0 |
T5 |
901 |
879 |
0 |
0 |
T16 |
1690 |
1667 |
0 |
0 |
T17 |
1810 |
1598 |
0 |
0 |
T18 |
3488 |
3246 |
0 |
0 |
T19 |
1768 |
1620 |
0 |
0 |
T20 |
931 |
892 |
0 |
0 |
T21 |
1919 |
1674 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172247520 |
169603757 |
0 |
2415 |
T1 |
364052 |
363400 |
0 |
3 |
T2 |
120484 |
120240 |
0 |
3 |
T4 |
573 |
552 |
0 |
3 |
T5 |
901 |
876 |
0 |
3 |
T16 |
1690 |
1664 |
0 |
3 |
T17 |
1810 |
1595 |
0 |
3 |
T18 |
3488 |
3243 |
0 |
3 |
T19 |
1768 |
1617 |
0 |
3 |
T20 |
931 |
889 |
0 |
3 |
T21 |
1919 |
1671 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172247520 |
19730 |
0 |
0 |
T1 |
364052 |
90 |
0 |
0 |
T2 |
120484 |
0 |
0 |
0 |
T3 |
85042 |
0 |
0 |
0 |
T9 |
0 |
295 |
0 |
0 |
T16 |
1690 |
26 |
0 |
0 |
T17 |
1810 |
36 |
0 |
0 |
T18 |
3488 |
0 |
0 |
0 |
T19 |
1768 |
21 |
0 |
0 |
T20 |
931 |
2 |
0 |
0 |
T21 |
1919 |
26 |
0 |
0 |
T22 |
1609 |
0 |
0 |
0 |
T27 |
0 |
4 |
0 |
0 |
T29 |
0 |
27 |
0 |
0 |
T30 |
0 |
27 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
524066189 |
521750623 |
0 |
0 |
T1 |
357452 |
357041 |
0 |
0 |
T2 |
663368 |
662799 |
0 |
0 |
T4 |
4773 |
4719 |
0 |
0 |
T5 |
5635 |
5537 |
0 |
0 |
T16 |
7047 |
6992 |
0 |
0 |
T17 |
1810 |
1726 |
0 |
0 |
T18 |
3671 |
3531 |
0 |
0 |
T19 |
1843 |
1731 |
0 |
0 |
T20 |
3726 |
3672 |
0 |
0 |
T21 |
1999 |
1887 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
524066189 |
521750623 |
0 |
0 |
T1 |
357452 |
357041 |
0 |
0 |
T2 |
663368 |
662799 |
0 |
0 |
T4 |
4773 |
4719 |
0 |
0 |
T5 |
5635 |
5537 |
0 |
0 |
T16 |
7047 |
6992 |
0 |
0 |
T17 |
1810 |
1726 |
0 |
0 |
T18 |
3671 |
3531 |
0 |
0 |
T19 |
1843 |
1731 |
0 |
0 |
T20 |
3726 |
3672 |
0 |
0 |
T21 |
1999 |
1887 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
492120848 |
489944106 |
0 |
0 |
T1 |
329895 |
329500 |
0 |
0 |
T2 |
527376 |
526831 |
0 |
0 |
T4 |
4581 |
4529 |
0 |
0 |
T5 |
5409 |
5316 |
0 |
0 |
T16 |
6765 |
6713 |
0 |
0 |
T17 |
1738 |
1658 |
0 |
0 |
T18 |
3523 |
3389 |
0 |
0 |
T19 |
1768 |
1661 |
0 |
0 |
T20 |
3577 |
3525 |
0 |
0 |
T21 |
1919 |
1811 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
492120848 |
489944106 |
0 |
0 |
T1 |
329895 |
329500 |
0 |
0 |
T2 |
527376 |
526831 |
0 |
0 |
T4 |
4581 |
4529 |
0 |
0 |
T5 |
5409 |
5316 |
0 |
0 |
T16 |
6765 |
6713 |
0 |
0 |
T17 |
1738 |
1658 |
0 |
0 |
T18 |
3523 |
3389 |
0 |
0 |
T19 |
1768 |
1661 |
0 |
0 |
T20 |
3577 |
3525 |
0 |
0 |
T21 |
1919 |
1811 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
245951634 |
245951634 |
0 |
0 |
T1 |
164774 |
164774 |
0 |
0 |
T2 |
263417 |
263417 |
0 |
0 |
T4 |
2265 |
2265 |
0 |
0 |
T5 |
2658 |
2658 |
0 |
0 |
T16 |
3820 |
3820 |
0 |
0 |
T17 |
865 |
865 |
0 |
0 |
T18 |
1695 |
1695 |
0 |
0 |
T19 |
881 |
881 |
0 |
0 |
T20 |
1768 |
1768 |
0 |
0 |
T21 |
998 |
998 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
245951634 |
245951634 |
0 |
0 |
T1 |
164774 |
164774 |
0 |
0 |
T2 |
263417 |
263417 |
0 |
0 |
T4 |
2265 |
2265 |
0 |
0 |
T5 |
2658 |
2658 |
0 |
0 |
T16 |
3820 |
3820 |
0 |
0 |
T17 |
865 |
865 |
0 |
0 |
T18 |
1695 |
1695 |
0 |
0 |
T19 |
881 |
881 |
0 |
0 |
T20 |
1768 |
1768 |
0 |
0 |
T21 |
998 |
998 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
122975165 |
122975165 |
0 |
0 |
T1 |
823867 |
823867 |
0 |
0 |
T2 |
131709 |
131709 |
0 |
0 |
T4 |
1132 |
1132 |
0 |
0 |
T5 |
1329 |
1329 |
0 |
0 |
T16 |
1910 |
1910 |
0 |
0 |
T17 |
432 |
432 |
0 |
0 |
T18 |
847 |
847 |
0 |
0 |
T19 |
440 |
440 |
0 |
0 |
T20 |
884 |
884 |
0 |
0 |
T21 |
498 |
498 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
122975165 |
122975165 |
0 |
0 |
T1 |
823867 |
823867 |
0 |
0 |
T2 |
131709 |
131709 |
0 |
0 |
T4 |
1132 |
1132 |
0 |
0 |
T5 |
1329 |
1329 |
0 |
0 |
T16 |
1910 |
1910 |
0 |
0 |
T17 |
432 |
432 |
0 |
0 |
T18 |
847 |
847 |
0 |
0 |
T19 |
440 |
440 |
0 |
0 |
T20 |
884 |
884 |
0 |
0 |
T21 |
498 |
498 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
251464983 |
250349458 |
0 |
0 |
T1 |
170139 |
169942 |
0 |
0 |
T2 |
304022 |
303749 |
0 |
0 |
T4 |
2290 |
2264 |
0 |
0 |
T5 |
2705 |
2658 |
0 |
0 |
T16 |
3382 |
3356 |
0 |
0 |
T17 |
868 |
829 |
0 |
0 |
T18 |
1761 |
1694 |
0 |
0 |
T19 |
884 |
831 |
0 |
0 |
T20 |
1788 |
1762 |
0 |
0 |
T21 |
960 |
906 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
251464983 |
250349458 |
0 |
0 |
T1 |
170139 |
169942 |
0 |
0 |
T2 |
304022 |
303749 |
0 |
0 |
T4 |
2290 |
2264 |
0 |
0 |
T5 |
2705 |
2658 |
0 |
0 |
T16 |
3382 |
3356 |
0 |
0 |
T17 |
868 |
829 |
0 |
0 |
T18 |
1761 |
1694 |
0 |
0 |
T19 |
884 |
831 |
0 |
0 |
T20 |
1788 |
1762 |
0 |
0 |
T21 |
960 |
906 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Assert Coverage for Instance : tb.dut.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172247520 |
169611074 |
0 |
0 |
T1 |
364052 |
363402 |
0 |
0 |
T2 |
120484 |
120258 |
0 |
0 |
T4 |
573 |
555 |
0 |
0 |
T5 |
901 |
879 |
0 |
0 |
T16 |
1690 |
1667 |
0 |
0 |
T17 |
1810 |
1598 |
0 |
0 |
T18 |
3488 |
3246 |
0 |
0 |
T19 |
1768 |
1620 |
0 |
0 |
T20 |
931 |
892 |
0 |
0 |
T21 |
1919 |
1674 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172247520 |
169603757 |
0 |
2415 |
T1 |
364052 |
363400 |
0 |
3 |
T2 |
120484 |
120240 |
0 |
3 |
T4 |
573 |
552 |
0 |
3 |
T5 |
901 |
876 |
0 |
3 |
T16 |
1690 |
1664 |
0 |
3 |
T17 |
1810 |
1595 |
0 |
3 |
T18 |
3488 |
3243 |
0 |
3 |
T19 |
1768 |
1617 |
0 |
3 |
T20 |
931 |
889 |
0 |
3 |
T21 |
1919 |
1671 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172247520 |
169611074 |
0 |
0 |
T1 |
364052 |
363402 |
0 |
0 |
T2 |
120484 |
120258 |
0 |
0 |
T4 |
573 |
555 |
0 |
0 |
T5 |
901 |
879 |
0 |
0 |
T16 |
1690 |
1667 |
0 |
0 |
T17 |
1810 |
1598 |
0 |
0 |
T18 |
3488 |
3246 |
0 |
0 |
T19 |
1768 |
1620 |
0 |
0 |
T20 |
931 |
892 |
0 |
0 |
T21 |
1919 |
1674 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172247520 |
169603757 |
0 |
2415 |
T1 |
364052 |
363400 |
0 |
3 |
T2 |
120484 |
120240 |
0 |
3 |
T4 |
573 |
552 |
0 |
3 |
T5 |
901 |
876 |
0 |
3 |
T16 |
1690 |
1664 |
0 |
3 |
T17 |
1810 |
1595 |
0 |
3 |
T18 |
3488 |
3243 |
0 |
3 |
T19 |
1768 |
1617 |
0 |
3 |
T20 |
931 |
889 |
0 |
3 |
T21 |
1919 |
1671 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172247520 |
169611074 |
0 |
0 |
T1 |
364052 |
363402 |
0 |
0 |
T2 |
120484 |
120258 |
0 |
0 |
T4 |
573 |
555 |
0 |
0 |
T5 |
901 |
879 |
0 |
0 |
T16 |
1690 |
1667 |
0 |
0 |
T17 |
1810 |
1598 |
0 |
0 |
T18 |
3488 |
3246 |
0 |
0 |
T19 |
1768 |
1620 |
0 |
0 |
T20 |
931 |
892 |
0 |
0 |
T21 |
1919 |
1674 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172247520 |
169603757 |
0 |
2415 |
T1 |
364052 |
363400 |
0 |
3 |
T2 |
120484 |
120240 |
0 |
3 |
T4 |
573 |
552 |
0 |
3 |
T5 |
901 |
876 |
0 |
3 |
T16 |
1690 |
1664 |
0 |
3 |
T17 |
1810 |
1595 |
0 |
3 |
T18 |
3488 |
3243 |
0 |
3 |
T19 |
1768 |
1617 |
0 |
3 |
T20 |
931 |
889 |
0 |
3 |
T21 |
1919 |
1671 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172247520 |
169611074 |
0 |
0 |
T1 |
364052 |
363402 |
0 |
0 |
T2 |
120484 |
120258 |
0 |
0 |
T4 |
573 |
555 |
0 |
0 |
T5 |
901 |
879 |
0 |
0 |
T16 |
1690 |
1667 |
0 |
0 |
T17 |
1810 |
1598 |
0 |
0 |
T18 |
3488 |
3246 |
0 |
0 |
T19 |
1768 |
1620 |
0 |
0 |
T20 |
931 |
892 |
0 |
0 |
T21 |
1919 |
1674 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172247520 |
169603757 |
0 |
2415 |
T1 |
364052 |
363400 |
0 |
3 |
T2 |
120484 |
120240 |
0 |
3 |
T4 |
573 |
552 |
0 |
3 |
T5 |
901 |
876 |
0 |
3 |
T16 |
1690 |
1664 |
0 |
3 |
T17 |
1810 |
1595 |
0 |
3 |
T18 |
3488 |
3243 |
0 |
3 |
T19 |
1768 |
1617 |
0 |
3 |
T20 |
931 |
889 |
0 |
3 |
T21 |
1919 |
1671 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172247520 |
169611074 |
0 |
0 |
T1 |
364052 |
363402 |
0 |
0 |
T2 |
120484 |
120258 |
0 |
0 |
T4 |
573 |
555 |
0 |
0 |
T5 |
901 |
879 |
0 |
0 |
T16 |
1690 |
1667 |
0 |
0 |
T17 |
1810 |
1598 |
0 |
0 |
T18 |
3488 |
3246 |
0 |
0 |
T19 |
1768 |
1620 |
0 |
0 |
T20 |
931 |
892 |
0 |
0 |
T21 |
1919 |
1674 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172247520 |
169603757 |
0 |
2415 |
T1 |
364052 |
363400 |
0 |
3 |
T2 |
120484 |
120240 |
0 |
3 |
T4 |
573 |
552 |
0 |
3 |
T5 |
901 |
876 |
0 |
3 |
T16 |
1690 |
1664 |
0 |
3 |
T17 |
1810 |
1595 |
0 |
3 |
T18 |
3488 |
3243 |
0 |
3 |
T19 |
1768 |
1617 |
0 |
3 |
T20 |
931 |
889 |
0 |
3 |
T21 |
1919 |
1671 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172247520 |
169611074 |
0 |
0 |
T1 |
364052 |
363402 |
0 |
0 |
T2 |
120484 |
120258 |
0 |
0 |
T4 |
573 |
555 |
0 |
0 |
T5 |
901 |
879 |
0 |
0 |
T16 |
1690 |
1667 |
0 |
0 |
T17 |
1810 |
1598 |
0 |
0 |
T18 |
3488 |
3246 |
0 |
0 |
T19 |
1768 |
1620 |
0 |
0 |
T20 |
931 |
892 |
0 |
0 |
T21 |
1919 |
1674 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172247520 |
169603757 |
0 |
2415 |
T1 |
364052 |
363400 |
0 |
3 |
T2 |
120484 |
120240 |
0 |
3 |
T4 |
573 |
552 |
0 |
3 |
T5 |
901 |
876 |
0 |
3 |
T16 |
1690 |
1664 |
0 |
3 |
T17 |
1810 |
1595 |
0 |
3 |
T18 |
3488 |
3243 |
0 |
3 |
T19 |
1768 |
1617 |
0 |
3 |
T20 |
931 |
889 |
0 |
3 |
T21 |
1919 |
1671 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172247520 |
169611074 |
0 |
0 |
T1 |
364052 |
363402 |
0 |
0 |
T2 |
120484 |
120258 |
0 |
0 |
T4 |
573 |
555 |
0 |
0 |
T5 |
901 |
879 |
0 |
0 |
T16 |
1690 |
1667 |
0 |
0 |
T17 |
1810 |
1598 |
0 |
0 |
T18 |
3488 |
3246 |
0 |
0 |
T19 |
1768 |
1620 |
0 |
0 |
T20 |
931 |
892 |
0 |
0 |
T21 |
1919 |
1674 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172247520 |
169611074 |
0 |
0 |
T1 |
364052 |
363402 |
0 |
0 |
T2 |
120484 |
120258 |
0 |
0 |
T4 |
573 |
555 |
0 |
0 |
T5 |
901 |
879 |
0 |
0 |
T16 |
1690 |
1667 |
0 |
0 |
T17 |
1810 |
1598 |
0 |
0 |
T18 |
3488 |
3246 |
0 |
0 |
T19 |
1768 |
1620 |
0 |
0 |
T20 |
931 |
892 |
0 |
0 |
T21 |
1919 |
1674 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172247520 |
169611074 |
0 |
0 |
T1 |
364052 |
363402 |
0 |
0 |
T2 |
120484 |
120258 |
0 |
0 |
T4 |
573 |
555 |
0 |
0 |
T5 |
901 |
879 |
0 |
0 |
T16 |
1690 |
1667 |
0 |
0 |
T17 |
1810 |
1598 |
0 |
0 |
T18 |
3488 |
3246 |
0 |
0 |
T19 |
1768 |
1620 |
0 |
0 |
T20 |
931 |
892 |
0 |
0 |
T21 |
1919 |
1674 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172247520 |
169611074 |
0 |
0 |
T1 |
364052 |
363402 |
0 |
0 |
T2 |
120484 |
120258 |
0 |
0 |
T4 |
573 |
555 |
0 |
0 |
T5 |
901 |
879 |
0 |
0 |
T16 |
1690 |
1667 |
0 |
0 |
T17 |
1810 |
1598 |
0 |
0 |
T18 |
3488 |
3246 |
0 |
0 |
T19 |
1768 |
1620 |
0 |
0 |
T20 |
931 |
892 |
0 |
0 |
T21 |
1919 |
1674 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172247520 |
169611074 |
0 |
0 |
T1 |
364052 |
363402 |
0 |
0 |
T2 |
120484 |
120258 |
0 |
0 |
T4 |
573 |
555 |
0 |
0 |
T5 |
901 |
879 |
0 |
0 |
T16 |
1690 |
1667 |
0 |
0 |
T17 |
1810 |
1598 |
0 |
0 |
T18 |
3488 |
3246 |
0 |
0 |
T19 |
1768 |
1620 |
0 |
0 |
T20 |
931 |
892 |
0 |
0 |
T21 |
1919 |
1674 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172247520 |
169611074 |
0 |
0 |
T1 |
364052 |
363402 |
0 |
0 |
T2 |
120484 |
120258 |
0 |
0 |
T4 |
573 |
555 |
0 |
0 |
T5 |
901 |
879 |
0 |
0 |
T16 |
1690 |
1667 |
0 |
0 |
T17 |
1810 |
1598 |
0 |
0 |
T18 |
3488 |
3246 |
0 |
0 |
T19 |
1768 |
1620 |
0 |
0 |
T20 |
931 |
892 |
0 |
0 |
T21 |
1919 |
1674 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172247520 |
169611074 |
0 |
0 |
T1 |
364052 |
363402 |
0 |
0 |
T2 |
120484 |
120258 |
0 |
0 |
T4 |
573 |
555 |
0 |
0 |
T5 |
901 |
879 |
0 |
0 |
T16 |
1690 |
1667 |
0 |
0 |
T17 |
1810 |
1598 |
0 |
0 |
T18 |
3488 |
3246 |
0 |
0 |
T19 |
1768 |
1620 |
0 |
0 |
T20 |
931 |
892 |
0 |
0 |
T21 |
1919 |
1674 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172247520 |
169611074 |
0 |
0 |
T1 |
364052 |
363402 |
0 |
0 |
T2 |
120484 |
120258 |
0 |
0 |
T4 |
573 |
555 |
0 |
0 |
T5 |
901 |
879 |
0 |
0 |
T16 |
1690 |
1667 |
0 |
0 |
T17 |
1810 |
1598 |
0 |
0 |
T18 |
3488 |
3246 |
0 |
0 |
T19 |
1768 |
1620 |
0 |
0 |
T20 |
931 |
892 |
0 |
0 |
T21 |
1919 |
1674 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T1 |
1 | Covered | T4,T5,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T1 |
1 | Covered | T4,T5,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T1 |
1 | Covered | T4,T5,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T1 |
1 | Covered | T4,T5,T1 |
Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
524066189 |
519538194 |
0 |
0 |
T1 |
357452 |
356802 |
0 |
0 |
T2 |
663368 |
662099 |
0 |
0 |
T4 |
4773 |
4619 |
0 |
0 |
T5 |
5635 |
5494 |
0 |
0 |
T16 |
7047 |
6949 |
0 |
0 |
T17 |
1810 |
1598 |
0 |
0 |
T18 |
3671 |
3416 |
0 |
0 |
T19 |
1843 |
1688 |
0 |
0 |
T20 |
3726 |
3572 |
0 |
0 |
T21 |
1999 |
1744 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
524066189 |
519530991 |
0 |
2415 |
T1 |
357452 |
356800 |
0 |
3 |
T2 |
663368 |
662081 |
0 |
3 |
T4 |
4773 |
4616 |
0 |
3 |
T5 |
5635 |
5491 |
0 |
3 |
T16 |
7047 |
6946 |
0 |
3 |
T17 |
1810 |
1595 |
0 |
3 |
T18 |
3671 |
3413 |
0 |
3 |
T19 |
1843 |
1685 |
0 |
3 |
T20 |
3726 |
3569 |
0 |
3 |
T21 |
1999 |
1741 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
524066189 |
33150 |
0 |
0 |
T1 |
357452 |
292 |
0 |
0 |
T2 |
663368 |
20 |
0 |
0 |
T4 |
4773 |
10 |
0 |
0 |
T5 |
5635 |
4 |
0 |
0 |
T16 |
7047 |
15 |
0 |
0 |
T17 |
1810 |
17 |
0 |
0 |
T18 |
3671 |
21 |
0 |
0 |
T19 |
1843 |
7 |
0 |
0 |
T20 |
3726 |
3 |
0 |
0 |
T21 |
1999 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
524066189 |
519538194 |
0 |
0 |
T1 |
357452 |
356802 |
0 |
0 |
T2 |
663368 |
662099 |
0 |
0 |
T4 |
4773 |
4619 |
0 |
0 |
T5 |
5635 |
5494 |
0 |
0 |
T16 |
7047 |
6949 |
0 |
0 |
T17 |
1810 |
1598 |
0 |
0 |
T18 |
3671 |
3416 |
0 |
0 |
T19 |
1843 |
1688 |
0 |
0 |
T20 |
3726 |
3572 |
0 |
0 |
T21 |
1999 |
1744 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
524066189 |
519538194 |
0 |
0 |
T1 |
357452 |
356802 |
0 |
0 |
T2 |
663368 |
662099 |
0 |
0 |
T4 |
4773 |
4619 |
0 |
0 |
T5 |
5635 |
5494 |
0 |
0 |
T16 |
7047 |
6949 |
0 |
0 |
T17 |
1810 |
1598 |
0 |
0 |
T18 |
3671 |
3416 |
0 |
0 |
T19 |
1843 |
1688 |
0 |
0 |
T20 |
3726 |
3572 |
0 |
0 |
T21 |
1999 |
1744 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T1 |
1 | Covered | T4,T5,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T1 |
1 | Covered | T4,T5,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T1 |
1 | Covered | T4,T5,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T1 |
1 | Covered | T4,T5,T1 |
Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
524066189 |
519538194 |
0 |
0 |
T1 |
357452 |
356802 |
0 |
0 |
T2 |
663368 |
662099 |
0 |
0 |
T4 |
4773 |
4619 |
0 |
0 |
T5 |
5635 |
5494 |
0 |
0 |
T16 |
7047 |
6949 |
0 |
0 |
T17 |
1810 |
1598 |
0 |
0 |
T18 |
3671 |
3416 |
0 |
0 |
T19 |
1843 |
1688 |
0 |
0 |
T20 |
3726 |
3572 |
0 |
0 |
T21 |
1999 |
1744 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
524066189 |
519530991 |
0 |
2415 |
T1 |
357452 |
356800 |
0 |
3 |
T2 |
663368 |
662081 |
0 |
3 |
T4 |
4773 |
4616 |
0 |
3 |
T5 |
5635 |
5491 |
0 |
3 |
T16 |
7047 |
6946 |
0 |
3 |
T17 |
1810 |
1595 |
0 |
3 |
T18 |
3671 |
3413 |
0 |
3 |
T19 |
1843 |
1685 |
0 |
3 |
T20 |
3726 |
3569 |
0 |
3 |
T21 |
1999 |
1741 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
524066189 |
33178 |
0 |
0 |
T1 |
357452 |
278 |
0 |
0 |
T2 |
663368 |
19 |
0 |
0 |
T4 |
4773 |
6 |
0 |
0 |
T5 |
5635 |
4 |
0 |
0 |
T16 |
7047 |
11 |
0 |
0 |
T17 |
1810 |
7 |
0 |
0 |
T18 |
3671 |
29 |
0 |
0 |
T19 |
1843 |
9 |
0 |
0 |
T20 |
3726 |
3 |
0 |
0 |
T21 |
1999 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
524066189 |
519538194 |
0 |
0 |
T1 |
357452 |
356802 |
0 |
0 |
T2 |
663368 |
662099 |
0 |
0 |
T4 |
4773 |
4619 |
0 |
0 |
T5 |
5635 |
5494 |
0 |
0 |
T16 |
7047 |
6949 |
0 |
0 |
T17 |
1810 |
1598 |
0 |
0 |
T18 |
3671 |
3416 |
0 |
0 |
T19 |
1843 |
1688 |
0 |
0 |
T20 |
3726 |
3572 |
0 |
0 |
T21 |
1999 |
1744 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
524066189 |
519538194 |
0 |
0 |
T1 |
357452 |
356802 |
0 |
0 |
T2 |
663368 |
662099 |
0 |
0 |
T4 |
4773 |
4619 |
0 |
0 |
T5 |
5635 |
5494 |
0 |
0 |
T16 |
7047 |
6949 |
0 |
0 |
T17 |
1810 |
1598 |
0 |
0 |
T18 |
3671 |
3416 |
0 |
0 |
T19 |
1843 |
1688 |
0 |
0 |
T20 |
3726 |
3572 |
0 |
0 |
T21 |
1999 |
1744 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T1 |
1 | Covered | T4,T5,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T1 |
1 | Covered | T4,T5,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T1 |
1 | Covered | T4,T5,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T1 |
1 | Covered | T4,T5,T1 |
Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
524066189 |
519538194 |
0 |
0 |
T1 |
357452 |
356802 |
0 |
0 |
T2 |
663368 |
662099 |
0 |
0 |
T4 |
4773 |
4619 |
0 |
0 |
T5 |
5635 |
5494 |
0 |
0 |
T16 |
7047 |
6949 |
0 |
0 |
T17 |
1810 |
1598 |
0 |
0 |
T18 |
3671 |
3416 |
0 |
0 |
T19 |
1843 |
1688 |
0 |
0 |
T20 |
3726 |
3572 |
0 |
0 |
T21 |
1999 |
1744 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
524066189 |
519530991 |
0 |
2415 |
T1 |
357452 |
356800 |
0 |
3 |
T2 |
663368 |
662081 |
0 |
3 |
T4 |
4773 |
4616 |
0 |
3 |
T5 |
5635 |
5491 |
0 |
3 |
T16 |
7047 |
6946 |
0 |
3 |
T17 |
1810 |
1595 |
0 |
3 |
T18 |
3671 |
3413 |
0 |
3 |
T19 |
1843 |
1685 |
0 |
3 |
T20 |
3726 |
3569 |
0 |
3 |
T21 |
1999 |
1741 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
524066189 |
32900 |
0 |
0 |
T1 |
357452 |
259 |
0 |
0 |
T2 |
663368 |
26 |
0 |
0 |
T4 |
4773 |
6 |
0 |
0 |
T5 |
5635 |
3 |
0 |
0 |
T16 |
7047 |
9 |
0 |
0 |
T17 |
1810 |
13 |
0 |
0 |
T18 |
3671 |
45 |
0 |
0 |
T19 |
1843 |
7 |
0 |
0 |
T20 |
3726 |
1 |
0 |
0 |
T21 |
1999 |
8 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
524066189 |
519538194 |
0 |
0 |
T1 |
357452 |
356802 |
0 |
0 |
T2 |
663368 |
662099 |
0 |
0 |
T4 |
4773 |
4619 |
0 |
0 |
T5 |
5635 |
5494 |
0 |
0 |
T16 |
7047 |
6949 |
0 |
0 |
T17 |
1810 |
1598 |
0 |
0 |
T18 |
3671 |
3416 |
0 |
0 |
T19 |
1843 |
1688 |
0 |
0 |
T20 |
3726 |
3572 |
0 |
0 |
T21 |
1999 |
1744 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
524066189 |
519538194 |
0 |
0 |
T1 |
357452 |
356802 |
0 |
0 |
T2 |
663368 |
662099 |
0 |
0 |
T4 |
4773 |
4619 |
0 |
0 |
T5 |
5635 |
5494 |
0 |
0 |
T16 |
7047 |
6949 |
0 |
0 |
T17 |
1810 |
1598 |
0 |
0 |
T18 |
3671 |
3416 |
0 |
0 |
T19 |
1843 |
1688 |
0 |
0 |
T20 |
3726 |
3572 |
0 |
0 |
T21 |
1999 |
1744 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T1 |
1 | Covered | T4,T5,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T1 |
1 | Covered | T4,T5,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T1 |
1 | Covered | T4,T5,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T1 |
1 | Covered | T4,T5,T1 |
Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
524066189 |
519538194 |
0 |
0 |
T1 |
357452 |
356802 |
0 |
0 |
T2 |
663368 |
662099 |
0 |
0 |
T4 |
4773 |
4619 |
0 |
0 |
T5 |
5635 |
5494 |
0 |
0 |
T16 |
7047 |
6949 |
0 |
0 |
T17 |
1810 |
1598 |
0 |
0 |
T18 |
3671 |
3416 |
0 |
0 |
T19 |
1843 |
1688 |
0 |
0 |
T20 |
3726 |
3572 |
0 |
0 |
T21 |
1999 |
1744 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
524066189 |
519530991 |
0 |
2415 |
T1 |
357452 |
356800 |
0 |
3 |
T2 |
663368 |
662081 |
0 |
3 |
T4 |
4773 |
4616 |
0 |
3 |
T5 |
5635 |
5491 |
0 |
3 |
T16 |
7047 |
6946 |
0 |
3 |
T17 |
1810 |
1595 |
0 |
3 |
T18 |
3671 |
3413 |
0 |
3 |
T19 |
1843 |
1685 |
0 |
3 |
T20 |
3726 |
3569 |
0 |
3 |
T21 |
1999 |
1741 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
524066189 |
33275 |
0 |
0 |
T1 |
357452 |
242 |
0 |
0 |
T2 |
663368 |
29 |
0 |
0 |
T4 |
4773 |
6 |
0 |
0 |
T5 |
5635 |
4 |
0 |
0 |
T16 |
7047 |
15 |
0 |
0 |
T17 |
1810 |
17 |
0 |
0 |
T18 |
3671 |
45 |
0 |
0 |
T19 |
1843 |
13 |
0 |
0 |
T20 |
3726 |
1 |
0 |
0 |
T21 |
1999 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
524066189 |
519538194 |
0 |
0 |
T1 |
357452 |
356802 |
0 |
0 |
T2 |
663368 |
662099 |
0 |
0 |
T4 |
4773 |
4619 |
0 |
0 |
T5 |
5635 |
5494 |
0 |
0 |
T16 |
7047 |
6949 |
0 |
0 |
T17 |
1810 |
1598 |
0 |
0 |
T18 |
3671 |
3416 |
0 |
0 |
T19 |
1843 |
1688 |
0 |
0 |
T20 |
3726 |
3572 |
0 |
0 |
T21 |
1999 |
1744 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
524066189 |
519538194 |
0 |
0 |
T1 |
357452 |
356802 |
0 |
0 |
T2 |
663368 |
662099 |
0 |
0 |
T4 |
4773 |
4619 |
0 |
0 |
T5 |
5635 |
5494 |
0 |
0 |
T16 |
7047 |
6949 |
0 |
0 |
T17 |
1810 |
1598 |
0 |
0 |
T18 |
3671 |
3416 |
0 |
0 |
T19 |
1843 |
1688 |
0 |
0 |
T20 |
3726 |
3572 |
0 |
0 |
T21 |
1999 |
1744 |
0 |
0 |