Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T2,T9

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	172247520	169484397	0	0
AllClkBypReqTrue_A	172247520	124300	0	0
IoClkBypReqFalse_A	172247520	169405499	0	2415
IoClkBypReqTrue_A	172247520	198444	0	0
LcClkBypAckFalse_A	172247520	169493220	0	0
LcClkBypAckTrue_A	172247520	115477	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172247520	169484397	0	0
T1	364052	363373	0	0
T2	120484	120252	0	0
T4	573	554	0	0
T5	901	878	0	0
T16	1690	1418	0	0
T17	1810	1516	0	0
T18	3488	3245	0	0
T19	1768	1480	0	0
T20	931	891	0	0
T21	1919	1550	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172247520	124300	0	0
T1	364052	283	0	0
T2	120484	0	0	0
T3	85042	0	0	0
T9	0	2336	0	0
T16	1690	248	0	0
T17	1810	81	0	0
T18	3488	0	0	0
T19	1768	139	0	0
T20	931	0	0	0
T21	1919	123	0	0
T22	1609	0	0	0
T27	0	45	0	0
T29	0	91	0	0
T30	0	168	0	0
T120	0	59	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172247520	169405499	0	2415
T1	364052	363324	0	3
T2	120484	120240	0	3
T4	573	552	0	3
T5	901	876	0	3
T16	1690	1349	0	3
T17	1810	1564	0	3
T18	3488	3243	0	3
T19	1768	1518	0	3
T20	931	859	0	3
T21	1919	1503	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172247520	198444	0	0
T1	364052	760	0	0
T2	120484	0	0	0
T3	85042	0	0	0
T9	0	3328	0	0
T16	1690	315	0	0
T17	1810	31	0	0
T18	3488	0	0	0
T19	1768	99	0	0
T20	931	30	0	0
T21	1919	168	0	0
T22	1609	0	0	0
T27	0	48	0	0
T29	0	135	0	0
T30	0	289	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172247520	169493220	0	0
T1	364052	363358	0	0
T2	120484	120252	0	0
T4	573	554	0	0
T5	901	878	0	0
T16	1690	1471	0	0
T17	1810	1570	0	0
T18	3488	3245	0	0
T19	1768	1561	0	0
T20	931	891	0	0
T21	1919	1552	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172247520	115477	0	0
T1	364052	429	0	0
T2	120484	0	0	0
T3	85042	0	0	0
T9	0	1857	0	0
T16	1690	195	0	0
T17	1810	27	0	0
T18	3488	0	0	0
T19	1768	58	0	0
T20	931	0	0	0
T21	1919	121	0	0
T22	1609	0	0	0
T27	0	33	0	0
T29	0	71	0	0
T30	0	178	0	0
T120	0	27	0	0