Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	2096266504	16105	0	0
TransStop_A	2096266504	8290	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2096266504	16105	0	0
T1	1429808	151	0	0
T2	2653476	4	0	0
T3	708672	0	0	0
T5	5635	1	0	0
T9	0	271	0	0
T11	0	575	0	0
T12	0	256	0	0
T16	28188	0	0	0
T17	7244	0	0	0
T18	14684	33	0	0
T19	7372	0	0	0
T20	14908	0	0	0
T21	8000	0	0	0
T22	4875	0	0	0
T26	0	23	0	0
T121	0	4	0	0
T122	0	42	0	0
T123	0	17	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2096266504	8290	0	0
T1	1429808	68	0	0
T2	2653476	4	0	0
T3	708672	0	0	0
T9	0	136	0	0
T11	0	296	0	0
T12	0	199	0	0
T16	28188	0	0	0
T17	7244	0	0	0
T18	14684	13	0	0
T19	7372	0	0	0
T20	14908	0	0	0
T21	8000	0	0	0
T22	6500	0	0	0
T26	0	11	0	0
T121	0	4	0	0
T122	0	23	0	0
T123	0	15	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	524066626	3981	0	0
TransStop_A	524066626	2048	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524066626	3981	0	0
T1	357452	42	0	0
T2	663369	1	0	0
T3	177168	0	0	0
T9	0	74	0	0
T11	0	144	0	0
T12	0	80	0	0
T16	7047	0	0	0
T17	1811	0	0	0
T18	3671	4	0	0
T19	1843	0	0	0
T20	3727	0	0	0
T21	2000	0	0	0
T22	1625	0	0	0
T26	0	3	0	0
T121	0	1	0	0
T122	0	11	0	0
T123	0	6	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524066626	2048	0	0
T1	357452	20	0	0
T2	663369	1	0	0
T3	177168	0	0	0
T9	0	38	0	0
T11	0	74	0	0
T12	0	41	0	0
T16	7047	0	0	0
T17	1811	0	0	0
T18	3671	2	0	0
T19	1843	0	0	0
T20	3727	0	0	0
T21	2000	0	0	0
T22	1625	0	0	0
T26	0	1	0	0
T121	0	1	0	0
T122	0	8	0	0
T123	0	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	524066626	3969	0	0
TransStop_A	524066626	2044	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524066626	3969	0	0
T1	357452	33	0	0
T2	663369	1	0	0
T3	177168	0	0	0
T5	5635	1	0	0
T9	0	65	0	0
T11	0	138	0	0
T16	7047	0	0	0
T17	1811	0	0	0
T18	3671	8	0	0
T19	1843	0	0	0
T20	3727	0	0	0
T21	2000	0	0	0
T26	0	4	0	0
T121	0	1	0	0
T122	0	11	0	0
T123	0	3	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524066626	2044	0	0
T1	357452	14	0	0
T2	663369	1	0	0
T3	177168	0	0	0
T9	0	31	0	0
T11	0	69	0	0
T12	0	58	0	0
T16	7047	0	0	0
T17	1811	0	0	0
T18	3671	4	0	0
T19	1843	0	0	0
T20	3727	0	0	0
T21	2000	0	0	0
T22	1625	0	0	0
T26	0	1	0	0
T121	0	1	0	0
T122	0	6	0	0
T123	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	524066626	4117	0	0
TransStop_A	524066626	2106	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524066626	4117	0	0
T1	357452	35	0	0
T2	663369	1	0	0
T3	177168	0	0	0
T9	0	65	0	0
T11	0	146	0	0
T12	0	91	0	0
T16	7047	0	0	0
T17	1811	0	0	0
T18	3671	12	0	0
T19	1843	0	0	0
T20	3727	0	0	0
T21	2000	0	0	0
T22	1625	0	0	0
T26	0	9	0	0
T121	0	1	0	0
T122	0	11	0	0
T123	0	3	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524066626	2106	0	0
T1	357452	16	0	0
T2	663369	1	0	0
T3	177168	0	0	0
T9	0	31	0	0
T11	0	73	0	0
T12	0	51	0	0
T16	7047	0	0	0
T17	1811	0	0	0
T18	3671	4	0	0
T19	1843	0	0	0
T20	3727	0	0	0
T21	2000	0	0	0
T22	1625	0	0	0
T26	0	5	0	0
T121	0	1	0	0
T122	0	5	0	0
T123	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	524066626	4038	0	0
TransStop_A	524066626	2092	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524066626	4038	0	0
T1	357452	41	0	0
T2	663369	1	0	0
T3	177168	0	0	0
T9	0	67	0	0
T11	0	147	0	0
T12	0	85	0	0
T16	7047	0	0	0
T17	1811	0	0	0
T18	3671	9	0	0
T19	1843	0	0	0
T20	3727	0	0	0
T21	2000	0	0	0
T22	1625	0	0	0
T26	0	7	0	0
T121	0	1	0	0
T122	0	9	0	0
T123	0	5	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524066626	2092	0	0
T1	357452	18	0	0
T2	663369	1	0	0
T3	177168	0	0	0
T9	0	36	0	0
T11	0	80	0	0
T12	0	49	0	0
T16	7047	0	0	0
T17	1811	0	0	0
T18	3671	3	0	0
T19	1843	0	0	0
T20	3727	0	0	0
T21	2000	0	0	0
T22	1625	0	0	0
T26	0	4	0	0
T121	0	1	0	0
T122	0	4	0	0
T123	0	4	0	0