Module Definition
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Module : prim_generic_clock_mux2
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_div2.u_step_down_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT4,T5,T1
10CoveredT1,T16,T17 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT4,T5,T1
10CoveredT1,T16,T17
11CoveredT1,T16,T17 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT1,T16,T17
10CoveredT4,T5,T1
11CoveredT4,T5,T1
Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 613899443 613897028 0 0
selKnown1 1476362544 1476360129 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 613899443 613897028 0 0
T1 1153391 1153390 0 0
T2 658543 658540 0 0
T4 5662 5659 0 0
T5 6645 6642 0 0
T16 9087 9084 0 0
T17 2126 2123 0 0
T18 4237 4234 0 0
T19 2152 2149 0 0
T20 4415 4412 0 0
T21 2402 2399 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1476362544 1476360129 0 0
T1 989685 989685 0 0
T2 1582128 1582125 0 0
T4 13743 13740 0 0
T5 16227 16224 0 0
T16 20295 20292 0 0
T17 5214 5211 0 0
T18 10569 10566 0 0
T19 5304 5301 0 0
T20 10731 10728 0 0
T21 5757 5754 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT4,T5,T1
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT4,T5,T1
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT4,T5,T1
11CoveredT4,T5,T1
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 245951634 245950829 0 0
selKnown1 492120848 492120043 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 245951634 245950829 0 0
T1 164774 164774 0 0
T2 263417 263416 0 0
T4 2265 2264 0 0
T5 2658 2657 0 0
T16 3820 3819 0 0
T17 865 864 0 0
T18 1695 1694 0 0
T19 881 880 0 0
T20 1768 1767 0 0
T21 998 997 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 492120848 492120043 0 0
T1 329895 329895 0 0
T2 527376 527375 0 0
T4 4581 4580 0 0
T5 5409 5408 0 0
T16 6765 6764 0 0
T17 1738 1737 0 0
T18 3523 3522 0 0
T19 1768 1767 0 0
T20 3577 3576 0 0
T21 1919 1918 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT4,T5,T1
10CoveredT1,T16,T17 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT4,T5,T1
10CoveredT1,T16,T17
11CoveredT1,T16,T17 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT1,T16,T17
10CoveredT4,T5,T1
11CoveredT4,T5,T1
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 244972644 244971839 0 0
selKnown1 492120848 492120043 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 244972644 244971839 0 0
T1 164750 164750 0 0
T2 263417 263416 0 0
T4 2265 2264 0 0
T5 2658 2657 0 0
T16 3357 3356 0 0
T17 829 828 0 0
T18 1695 1694 0 0
T19 831 830 0 0
T20 1763 1762 0 0
T21 906 905 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 492120848 492120043 0 0
T1 329895 329895 0 0
T2 527376 527375 0 0
T4 4581 4580 0 0
T5 5409 5408 0 0
T16 6765 6764 0 0
T17 1738 1737 0 0
T18 3523 3522 0 0
T19 1768 1767 0 0
T20 3577 3576 0 0
T21 1919 1918 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT4,T5,T1
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT4,T5,T1
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT4,T5,T1
11CoveredT4,T5,T1
Assert Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 122975165 122974360 0 0
selKnown1 492120848 492120043 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 122975165 122974360 0 0
T1 823867 823866 0 0
T2 131709 131708 0 0
T4 1132 1131 0 0
T5 1329 1328 0 0
T16 1910 1909 0 0
T17 432 431 0 0
T18 847 846 0 0
T19 440 439 0 0
T20 884 883 0 0
T21 498 497 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 492120848 492120043 0 0
T1 329895 329895 0 0
T2 527376 527375 0 0
T4 4581 4580 0 0
T5 5409 5408 0 0
T16 6765 6764 0 0
T17 1738 1737 0 0
T18 3523 3522 0 0
T19 1768 1767 0 0
T20 3577 3576 0 0
T21 1919 1918 0 0

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