Module Definition
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Module : clkmgr_lost_calib_regwen_sva_if
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if 100.00 100.00



Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
RegwenOff_A 172247520 20687853 0 61


RegwenOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 172247520 20687853 0 61
T1 364052 120167 0 0
T2 120484 7929 0 1
T3 85042 18353 0 1
T9 0 349811 0 0
T10 0 6325 0 1
T11 0 138616 0 0
T12 0 130939 0 0
T13 0 628375 0 0
T14 0 857697 0 0
T15 0 25358 0 0
T16 1690 0 0 0
T17 1810 0 0 0
T18 3488 0 0 0
T19 1768 0 0 0
T20 931 0 0 0
T21 1919 0 0 0
T22 1609 0 0 0
T80 0 0 0 1
T124 0 0 0 1
T125 0 0 0 1
T126 0 0 0 1
T127 0 0 0 1
T128 0 0 0 1
T129 0 0 0 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%