Line Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Module :
prim_pulse_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Module :
prim_pulse_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
945911 |
0 |
0 |
T1 |
2369588 |
4924 |
0 |
0 |
T2 |
2233188 |
2054 |
0 |
0 |
T3 |
729801 |
362 |
0 |
0 |
T9 |
0 |
8636 |
0 |
0 |
T10 |
0 |
490 |
0 |
0 |
T11 |
0 |
17452 |
0 |
0 |
T16 |
28872 |
0 |
0 |
0 |
T17 |
8385 |
0 |
0 |
0 |
T18 |
16614 |
0 |
0 |
0 |
T19 |
8462 |
0 |
0 |
0 |
T20 |
14422 |
0 |
0 |
0 |
T21 |
9329 |
0 |
0 |
0 |
T22 |
7482 |
0 |
0 |
0 |
T23 |
0 |
198 |
0 |
0 |
T24 |
0 |
736 |
0 |
0 |
T31 |
0 |
386 |
0 |
0 |
T32 |
0 |
644 |
0 |
0 |
T65 |
21766 |
3 |
0 |
0 |
T66 |
11424 |
2 |
0 |
0 |
T67 |
16800 |
3 |
0 |
0 |
T68 |
7218 |
3 |
0 |
0 |
T70 |
20174 |
3 |
0 |
0 |
T83 |
7257 |
1 |
0 |
0 |
T85 |
6559 |
1 |
0 |
0 |
T130 |
2954 |
1 |
0 |
0 |
T131 |
30520 |
2 |
0 |
0 |
T132 |
6543 |
1 |
0 |
0 |
T133 |
26276 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
944128 |
0 |
0 |
T1 |
1537954 |
4924 |
0 |
0 |
T2 |
512693 |
2054 |
0 |
0 |
T3 |
256553 |
362 |
0 |
0 |
T9 |
0 |
8639 |
0 |
0 |
T10 |
0 |
490 |
0 |
0 |
T11 |
0 |
17455 |
0 |
0 |
T16 |
9172 |
0 |
0 |
0 |
T17 |
4989 |
0 |
0 |
0 |
T18 |
9695 |
0 |
0 |
0 |
T19 |
4929 |
0 |
0 |
0 |
T20 |
4670 |
0 |
0 |
0 |
T21 |
5392 |
0 |
0 |
0 |
T22 |
4438 |
0 |
0 |
0 |
T23 |
0 |
198 |
0 |
0 |
T24 |
0 |
736 |
0 |
0 |
T31 |
0 |
386 |
0 |
0 |
T32 |
0 |
644 |
0 |
0 |
T65 |
14984 |
3 |
0 |
0 |
T66 |
11782 |
2 |
0 |
0 |
T67 |
15506 |
3 |
0 |
0 |
T68 |
12606 |
3 |
0 |
0 |
T70 |
8296 |
3 |
0 |
0 |
T83 |
6945 |
1 |
0 |
0 |
T85 |
12744 |
1 |
0 |
0 |
T130 |
5406 |
1 |
0 |
0 |
T131 |
13394 |
2 |
0 |
0 |
T132 |
2803 |
1 |
0 |
0 |
T133 |
23414 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
494688399 |
25482 |
0 |
0 |
T1 |
329895 |
230 |
0 |
0 |
T2 |
527376 |
106 |
0 |
0 |
T3 |
170075 |
30 |
0 |
0 |
T9 |
0 |
445 |
0 |
0 |
T10 |
0 |
34 |
0 |
0 |
T11 |
0 |
851 |
0 |
0 |
T16 |
6765 |
0 |
0 |
0 |
T17 |
1738 |
0 |
0 |
0 |
T18 |
3523 |
0 |
0 |
0 |
T19 |
1768 |
0 |
0 |
0 |
T20 |
3577 |
0 |
0 |
0 |
T21 |
1919 |
0 |
0 |
0 |
T22 |
1560 |
0 |
0 |
0 |
T23 |
0 |
10 |
0 |
0 |
T24 |
0 |
28 |
0 |
0 |
T31 |
0 |
14 |
0 |
0 |
T32 |
0 |
24 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
173139840 |
25482 |
0 |
0 |
T1 |
364052 |
230 |
0 |
0 |
T2 |
120484 |
106 |
0 |
0 |
T3 |
85042 |
30 |
0 |
0 |
T9 |
0 |
445 |
0 |
0 |
T10 |
0 |
34 |
0 |
0 |
T11 |
0 |
851 |
0 |
0 |
T16 |
1690 |
0 |
0 |
0 |
T17 |
1810 |
0 |
0 |
0 |
T18 |
3488 |
0 |
0 |
0 |
T19 |
1768 |
0 |
0 |
0 |
T20 |
931 |
0 |
0 |
0 |
T21 |
1919 |
0 |
0 |
0 |
T22 |
1609 |
0 |
0 |
0 |
T23 |
0 |
10 |
0 |
0 |
T24 |
0 |
28 |
0 |
0 |
T31 |
0 |
14 |
0 |
0 |
T32 |
0 |
24 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
494688399 |
31020 |
0 |
0 |
T1 |
329895 |
235 |
0 |
0 |
T2 |
527376 |
106 |
0 |
0 |
T3 |
170075 |
30 |
0 |
0 |
T9 |
0 |
458 |
0 |
0 |
T10 |
0 |
34 |
0 |
0 |
T11 |
0 |
862 |
0 |
0 |
T16 |
6765 |
0 |
0 |
0 |
T17 |
1738 |
0 |
0 |
0 |
T18 |
3523 |
0 |
0 |
0 |
T19 |
1768 |
0 |
0 |
0 |
T20 |
3577 |
0 |
0 |
0 |
T21 |
1919 |
0 |
0 |
0 |
T22 |
1560 |
0 |
0 |
0 |
T23 |
0 |
10 |
0 |
0 |
T24 |
0 |
28 |
0 |
0 |
T31 |
0 |
14 |
0 |
0 |
T32 |
0 |
24 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
173139840 |
31037 |
0 |
0 |
T1 |
364052 |
235 |
0 |
0 |
T2 |
120484 |
106 |
0 |
0 |
T3 |
85042 |
30 |
0 |
0 |
T9 |
0 |
458 |
0 |
0 |
T10 |
0 |
34 |
0 |
0 |
T11 |
0 |
862 |
0 |
0 |
T16 |
1690 |
0 |
0 |
0 |
T17 |
1810 |
0 |
0 |
0 |
T18 |
3488 |
0 |
0 |
0 |
T19 |
1768 |
0 |
0 |
0 |
T20 |
931 |
0 |
0 |
0 |
T21 |
1919 |
0 |
0 |
0 |
T22 |
1609 |
0 |
0 |
0 |
T23 |
0 |
10 |
0 |
0 |
T24 |
0 |
28 |
0 |
0 |
T31 |
0 |
14 |
0 |
0 |
T32 |
0 |
24 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
173139840 |
31009 |
0 |
0 |
T1 |
364052 |
235 |
0 |
0 |
T2 |
120484 |
106 |
0 |
0 |
T3 |
85042 |
30 |
0 |
0 |
T9 |
0 |
458 |
0 |
0 |
T10 |
0 |
34 |
0 |
0 |
T11 |
0 |
862 |
0 |
0 |
T16 |
1690 |
0 |
0 |
0 |
T17 |
1810 |
0 |
0 |
0 |
T18 |
3488 |
0 |
0 |
0 |
T19 |
1768 |
0 |
0 |
0 |
T20 |
931 |
0 |
0 |
0 |
T21 |
1919 |
0 |
0 |
0 |
T22 |
1609 |
0 |
0 |
0 |
T23 |
0 |
10 |
0 |
0 |
T24 |
0 |
28 |
0 |
0 |
T31 |
0 |
14 |
0 |
0 |
T32 |
0 |
24 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
494688399 |
31022 |
0 |
0 |
T1 |
329895 |
235 |
0 |
0 |
T2 |
527376 |
106 |
0 |
0 |
T3 |
170075 |
30 |
0 |
0 |
T9 |
0 |
458 |
0 |
0 |
T10 |
0 |
34 |
0 |
0 |
T11 |
0 |
862 |
0 |
0 |
T16 |
6765 |
0 |
0 |
0 |
T17 |
1738 |
0 |
0 |
0 |
T18 |
3523 |
0 |
0 |
0 |
T19 |
1768 |
0 |
0 |
0 |
T20 |
3577 |
0 |
0 |
0 |
T21 |
1919 |
0 |
0 |
0 |
T22 |
1560 |
0 |
0 |
0 |
T23 |
0 |
10 |
0 |
0 |
T24 |
0 |
28 |
0 |
0 |
T31 |
0 |
14 |
0 |
0 |
T32 |
0 |
24 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
247188951 |
25482 |
0 |
0 |
T1 |
164774 |
230 |
0 |
0 |
T2 |
263417 |
106 |
0 |
0 |
T3 |
85005 |
30 |
0 |
0 |
T9 |
0 |
445 |
0 |
0 |
T10 |
0 |
34 |
0 |
0 |
T11 |
0 |
851 |
0 |
0 |
T16 |
3820 |
0 |
0 |
0 |
T17 |
865 |
0 |
0 |
0 |
T18 |
1695 |
0 |
0 |
0 |
T19 |
881 |
0 |
0 |
0 |
T20 |
1768 |
0 |
0 |
0 |
T21 |
998 |
0 |
0 |
0 |
T22 |
768 |
0 |
0 |
0 |
T23 |
0 |
10 |
0 |
0 |
T24 |
0 |
28 |
0 |
0 |
T31 |
0 |
14 |
0 |
0 |
T32 |
0 |
24 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
173139840 |
25482 |
0 |
0 |
T1 |
364052 |
230 |
0 |
0 |
T2 |
120484 |
106 |
0 |
0 |
T3 |
85042 |
30 |
0 |
0 |
T9 |
0 |
445 |
0 |
0 |
T10 |
0 |
34 |
0 |
0 |
T11 |
0 |
851 |
0 |
0 |
T16 |
1690 |
0 |
0 |
0 |
T17 |
1810 |
0 |
0 |
0 |
T18 |
3488 |
0 |
0 |
0 |
T19 |
1768 |
0 |
0 |
0 |
T20 |
931 |
0 |
0 |
0 |
T21 |
1919 |
0 |
0 |
0 |
T22 |
1609 |
0 |
0 |
0 |
T23 |
0 |
10 |
0 |
0 |
T24 |
0 |
28 |
0 |
0 |
T31 |
0 |
14 |
0 |
0 |
T32 |
0 |
24 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
247188951 |
31108 |
0 |
0 |
T1 |
164774 |
235 |
0 |
0 |
T2 |
263417 |
106 |
0 |
0 |
T3 |
85005 |
30 |
0 |
0 |
T9 |
0 |
458 |
0 |
0 |
T10 |
0 |
34 |
0 |
0 |
T11 |
0 |
862 |
0 |
0 |
T16 |
3820 |
0 |
0 |
0 |
T17 |
865 |
0 |
0 |
0 |
T18 |
1695 |
0 |
0 |
0 |
T19 |
881 |
0 |
0 |
0 |
T20 |
1768 |
0 |
0 |
0 |
T21 |
998 |
0 |
0 |
0 |
T22 |
768 |
0 |
0 |
0 |
T23 |
0 |
10 |
0 |
0 |
T24 |
0 |
28 |
0 |
0 |
T31 |
0 |
14 |
0 |
0 |
T32 |
0 |
24 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
173139840 |
31132 |
0 |
0 |
T1 |
364052 |
235 |
0 |
0 |
T2 |
120484 |
106 |
0 |
0 |
T3 |
85042 |
30 |
0 |
0 |
T9 |
0 |
458 |
0 |
0 |
T10 |
0 |
34 |
0 |
0 |
T11 |
0 |
862 |
0 |
0 |
T16 |
1690 |
0 |
0 |
0 |
T17 |
1810 |
0 |
0 |
0 |
T18 |
3488 |
0 |
0 |
0 |
T19 |
1768 |
0 |
0 |
0 |
T20 |
931 |
0 |
0 |
0 |
T21 |
1919 |
0 |
0 |
0 |
T22 |
1609 |
0 |
0 |
0 |
T23 |
0 |
10 |
0 |
0 |
T24 |
0 |
28 |
0 |
0 |
T31 |
0 |
14 |
0 |
0 |
T32 |
0 |
24 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
173139840 |
31101 |
0 |
0 |
T1 |
364052 |
235 |
0 |
0 |
T2 |
120484 |
106 |
0 |
0 |
T3 |
85042 |
30 |
0 |
0 |
T9 |
0 |
458 |
0 |
0 |
T10 |
0 |
34 |
0 |
0 |
T11 |
0 |
862 |
0 |
0 |
T16 |
1690 |
0 |
0 |
0 |
T17 |
1810 |
0 |
0 |
0 |
T18 |
3488 |
0 |
0 |
0 |
T19 |
1768 |
0 |
0 |
0 |
T20 |
931 |
0 |
0 |
0 |
T21 |
1919 |
0 |
0 |
0 |
T22 |
1609 |
0 |
0 |
0 |
T23 |
0 |
10 |
0 |
0 |
T24 |
0 |
28 |
0 |
0 |
T31 |
0 |
14 |
0 |
0 |
T32 |
0 |
24 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
247188951 |
31110 |
0 |
0 |
T1 |
164774 |
235 |
0 |
0 |
T2 |
263417 |
106 |
0 |
0 |
T3 |
85005 |
30 |
0 |
0 |
T9 |
0 |
458 |
0 |
0 |
T10 |
0 |
34 |
0 |
0 |
T11 |
0 |
862 |
0 |
0 |
T16 |
3820 |
0 |
0 |
0 |
T17 |
865 |
0 |
0 |
0 |
T18 |
1695 |
0 |
0 |
0 |
T19 |
881 |
0 |
0 |
0 |
T20 |
1768 |
0 |
0 |
0 |
T21 |
998 |
0 |
0 |
0 |
T22 |
768 |
0 |
0 |
0 |
T23 |
0 |
10 |
0 |
0 |
T24 |
0 |
28 |
0 |
0 |
T31 |
0 |
14 |
0 |
0 |
T32 |
0 |
24 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123593830 |
25482 |
0 |
0 |
T1 |
823867 |
230 |
0 |
0 |
T2 |
131709 |
106 |
0 |
0 |
T3 |
42502 |
30 |
0 |
0 |
T9 |
0 |
445 |
0 |
0 |
T10 |
0 |
34 |
0 |
0 |
T11 |
0 |
851 |
0 |
0 |
T16 |
1910 |
0 |
0 |
0 |
T17 |
432 |
0 |
0 |
0 |
T18 |
847 |
0 |
0 |
0 |
T19 |
440 |
0 |
0 |
0 |
T20 |
884 |
0 |
0 |
0 |
T21 |
498 |
0 |
0 |
0 |
T22 |
384 |
0 |
0 |
0 |
T23 |
0 |
10 |
0 |
0 |
T24 |
0 |
28 |
0 |
0 |
T31 |
0 |
14 |
0 |
0 |
T32 |
0 |
24 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
173139840 |
25482 |
0 |
0 |
T1 |
364052 |
230 |
0 |
0 |
T2 |
120484 |
106 |
0 |
0 |
T3 |
85042 |
30 |
0 |
0 |
T9 |
0 |
445 |
0 |
0 |
T10 |
0 |
34 |
0 |
0 |
T11 |
0 |
851 |
0 |
0 |
T16 |
1690 |
0 |
0 |
0 |
T17 |
1810 |
0 |
0 |
0 |
T18 |
3488 |
0 |
0 |
0 |
T19 |
1768 |
0 |
0 |
0 |
T20 |
931 |
0 |
0 |
0 |
T21 |
1919 |
0 |
0 |
0 |
T22 |
1609 |
0 |
0 |
0 |
T23 |
0 |
10 |
0 |
0 |
T24 |
0 |
28 |
0 |
0 |
T31 |
0 |
14 |
0 |
0 |
T32 |
0 |
24 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123593830 |
31110 |
0 |
0 |
T1 |
823867 |
235 |
0 |
0 |
T2 |
131709 |
106 |
0 |
0 |
T3 |
42502 |
30 |
0 |
0 |
T9 |
0 |
458 |
0 |
0 |
T10 |
0 |
34 |
0 |
0 |
T11 |
0 |
862 |
0 |
0 |
T16 |
1910 |
0 |
0 |
0 |
T17 |
432 |
0 |
0 |
0 |
T18 |
847 |
0 |
0 |
0 |
T19 |
440 |
0 |
0 |
0 |
T20 |
884 |
0 |
0 |
0 |
T21 |
498 |
0 |
0 |
0 |
T22 |
384 |
0 |
0 |
0 |
T23 |
0 |
10 |
0 |
0 |
T24 |
0 |
28 |
0 |
0 |
T31 |
0 |
14 |
0 |
0 |
T32 |
0 |
24 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
173139840 |
31139 |
0 |
0 |
T1 |
364052 |
235 |
0 |
0 |
T2 |
120484 |
106 |
0 |
0 |
T3 |
85042 |
30 |
0 |
0 |
T9 |
0 |
458 |
0 |
0 |
T10 |
0 |
34 |
0 |
0 |
T11 |
0 |
862 |
0 |
0 |
T16 |
1690 |
0 |
0 |
0 |
T17 |
1810 |
0 |
0 |
0 |
T18 |
3488 |
0 |
0 |
0 |
T19 |
1768 |
0 |
0 |
0 |
T20 |
931 |
0 |
0 |
0 |
T21 |
1919 |
0 |
0 |
0 |
T22 |
1609 |
0 |
0 |
0 |
T23 |
0 |
10 |
0 |
0 |
T24 |
0 |
28 |
0 |
0 |
T31 |
0 |
14 |
0 |
0 |
T32 |
0 |
24 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
173139840 |
31107 |
0 |
0 |
T1 |
364052 |
235 |
0 |
0 |
T2 |
120484 |
106 |
0 |
0 |
T3 |
85042 |
30 |
0 |
0 |
T9 |
0 |
458 |
0 |
0 |
T10 |
0 |
34 |
0 |
0 |
T11 |
0 |
862 |
0 |
0 |
T16 |
1690 |
0 |
0 |
0 |
T17 |
1810 |
0 |
0 |
0 |
T18 |
3488 |
0 |
0 |
0 |
T19 |
1768 |
0 |
0 |
0 |
T20 |
931 |
0 |
0 |
0 |
T21 |
1919 |
0 |
0 |
0 |
T22 |
1609 |
0 |
0 |
0 |
T23 |
0 |
10 |
0 |
0 |
T24 |
0 |
28 |
0 |
0 |
T31 |
0 |
14 |
0 |
0 |
T32 |
0 |
24 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123593830 |
31116 |
0 |
0 |
T1 |
823867 |
235 |
0 |
0 |
T2 |
131709 |
106 |
0 |
0 |
T3 |
42502 |
30 |
0 |
0 |
T9 |
0 |
458 |
0 |
0 |
T10 |
0 |
34 |
0 |
0 |
T11 |
0 |
862 |
0 |
0 |
T16 |
1910 |
0 |
0 |
0 |
T17 |
432 |
0 |
0 |
0 |
T18 |
847 |
0 |
0 |
0 |
T19 |
440 |
0 |
0 |
0 |
T20 |
884 |
0 |
0 |
0 |
T21 |
498 |
0 |
0 |
0 |
T22 |
384 |
0 |
0 |
0 |
T23 |
0 |
10 |
0 |
0 |
T24 |
0 |
28 |
0 |
0 |
T31 |
0 |
14 |
0 |
0 |
T32 |
0 |
24 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526740827 |
25482 |
0 |
0 |
T1 |
357452 |
230 |
0 |
0 |
T2 |
663368 |
106 |
0 |
0 |
T3 |
177167 |
30 |
0 |
0 |
T9 |
0 |
445 |
0 |
0 |
T10 |
0 |
34 |
0 |
0 |
T11 |
0 |
851 |
0 |
0 |
T16 |
7047 |
0 |
0 |
0 |
T17 |
1810 |
0 |
0 |
0 |
T18 |
3671 |
0 |
0 |
0 |
T19 |
1843 |
0 |
0 |
0 |
T20 |
3726 |
0 |
0 |
0 |
T21 |
1999 |
0 |
0 |
0 |
T22 |
1625 |
0 |
0 |
0 |
T23 |
0 |
10 |
0 |
0 |
T24 |
0 |
28 |
0 |
0 |
T31 |
0 |
14 |
0 |
0 |
T32 |
0 |
24 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
173139840 |
25482 |
0 |
0 |
T1 |
364052 |
230 |
0 |
0 |
T2 |
120484 |
106 |
0 |
0 |
T3 |
85042 |
30 |
0 |
0 |
T9 |
0 |
445 |
0 |
0 |
T10 |
0 |
34 |
0 |
0 |
T11 |
0 |
851 |
0 |
0 |
T16 |
1690 |
0 |
0 |
0 |
T17 |
1810 |
0 |
0 |
0 |
T18 |
3488 |
0 |
0 |
0 |
T19 |
1768 |
0 |
0 |
0 |
T20 |
931 |
0 |
0 |
0 |
T21 |
1919 |
0 |
0 |
0 |
T22 |
1609 |
0 |
0 |
0 |
T23 |
0 |
10 |
0 |
0 |
T24 |
0 |
28 |
0 |
0 |
T31 |
0 |
14 |
0 |
0 |
T32 |
0 |
24 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526740827 |
31020 |
0 |
0 |
T1 |
357452 |
235 |
0 |
0 |
T2 |
663368 |
106 |
0 |
0 |
T3 |
177167 |
30 |
0 |
0 |
T9 |
0 |
458 |
0 |
0 |
T10 |
0 |
34 |
0 |
0 |
T11 |
0 |
862 |
0 |
0 |
T16 |
7047 |
0 |
0 |
0 |
T17 |
1810 |
0 |
0 |
0 |
T18 |
3671 |
0 |
0 |
0 |
T19 |
1843 |
0 |
0 |
0 |
T20 |
3726 |
0 |
0 |
0 |
T21 |
1999 |
0 |
0 |
0 |
T22 |
1625 |
0 |
0 |
0 |
T23 |
0 |
10 |
0 |
0 |
T24 |
0 |
28 |
0 |
0 |
T31 |
0 |
14 |
0 |
0 |
T32 |
0 |
24 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
173139840 |
31035 |
0 |
0 |
T1 |
364052 |
235 |
0 |
0 |
T2 |
120484 |
106 |
0 |
0 |
T3 |
85042 |
30 |
0 |
0 |
T9 |
0 |
458 |
0 |
0 |
T10 |
0 |
34 |
0 |
0 |
T11 |
0 |
862 |
0 |
0 |
T16 |
1690 |
0 |
0 |
0 |
T17 |
1810 |
0 |
0 |
0 |
T18 |
3488 |
0 |
0 |
0 |
T19 |
1768 |
0 |
0 |
0 |
T20 |
931 |
0 |
0 |
0 |
T21 |
1919 |
0 |
0 |
0 |
T22 |
1609 |
0 |
0 |
0 |
T23 |
0 |
10 |
0 |
0 |
T24 |
0 |
28 |
0 |
0 |
T31 |
0 |
14 |
0 |
0 |
T32 |
0 |
24 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
173139840 |
31010 |
0 |
0 |
T1 |
364052 |
235 |
0 |
0 |
T2 |
120484 |
106 |
0 |
0 |
T3 |
85042 |
30 |
0 |
0 |
T9 |
0 |
458 |
0 |
0 |
T10 |
0 |
34 |
0 |
0 |
T11 |
0 |
862 |
0 |
0 |
T16 |
1690 |
0 |
0 |
0 |
T17 |
1810 |
0 |
0 |
0 |
T18 |
3488 |
0 |
0 |
0 |
T19 |
1768 |
0 |
0 |
0 |
T20 |
931 |
0 |
0 |
0 |
T21 |
1919 |
0 |
0 |
0 |
T22 |
1609 |
0 |
0 |
0 |
T23 |
0 |
10 |
0 |
0 |
T24 |
0 |
28 |
0 |
0 |
T31 |
0 |
14 |
0 |
0 |
T32 |
0 |
24 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526740827 |
31022 |
0 |
0 |
T1 |
357452 |
235 |
0 |
0 |
T2 |
663368 |
106 |
0 |
0 |
T3 |
177167 |
30 |
0 |
0 |
T9 |
0 |
458 |
0 |
0 |
T10 |
0 |
34 |
0 |
0 |
T11 |
0 |
862 |
0 |
0 |
T16 |
7047 |
0 |
0 |
0 |
T17 |
1810 |
0 |
0 |
0 |
T18 |
3671 |
0 |
0 |
0 |
T19 |
1843 |
0 |
0 |
0 |
T20 |
3726 |
0 |
0 |
0 |
T21 |
1999 |
0 |
0 |
0 |
T22 |
1625 |
0 |
0 |
0 |
T23 |
0 |
10 |
0 |
0 |
T24 |
0 |
28 |
0 |
0 |
T31 |
0 |
14 |
0 |
0 |
T32 |
0 |
24 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
252748778 |
25044 |
0 |
0 |
T1 |
170139 |
230 |
0 |
0 |
T2 |
304022 |
106 |
0 |
0 |
T3 |
85042 |
30 |
0 |
0 |
T9 |
0 |
445 |
0 |
0 |
T10 |
0 |
34 |
0 |
0 |
T11 |
0 |
851 |
0 |
0 |
T16 |
3382 |
0 |
0 |
0 |
T17 |
868 |
0 |
0 |
0 |
T18 |
1761 |
0 |
0 |
0 |
T19 |
884 |
0 |
0 |
0 |
T20 |
1788 |
0 |
0 |
0 |
T21 |
960 |
0 |
0 |
0 |
T22 |
780 |
0 |
0 |
0 |
T23 |
0 |
10 |
0 |
0 |
T24 |
0 |
28 |
0 |
0 |
T31 |
0 |
14 |
0 |
0 |
T32 |
0 |
24 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
173139840 |
25482 |
0 |
0 |
T1 |
364052 |
230 |
0 |
0 |
T2 |
120484 |
106 |
0 |
0 |
T3 |
85042 |
30 |
0 |
0 |
T9 |
0 |
445 |
0 |
0 |
T10 |
0 |
34 |
0 |
0 |
T11 |
0 |
851 |
0 |
0 |
T16 |
1690 |
0 |
0 |
0 |
T17 |
1810 |
0 |
0 |
0 |
T18 |
3488 |
0 |
0 |
0 |
T19 |
1768 |
0 |
0 |
0 |
T20 |
931 |
0 |
0 |
0 |
T21 |
1919 |
0 |
0 |
0 |
T22 |
1609 |
0 |
0 |
0 |
T23 |
0 |
10 |
0 |
0 |
T24 |
0 |
28 |
0 |
0 |
T31 |
0 |
14 |
0 |
0 |
T32 |
0 |
24 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
252748778 |
30995 |
0 |
0 |
T1 |
170139 |
235 |
0 |
0 |
T2 |
304022 |
106 |
0 |
0 |
T3 |
85042 |
30 |
0 |
0 |
T9 |
0 |
458 |
0 |
0 |
T10 |
0 |
34 |
0 |
0 |
T11 |
0 |
862 |
0 |
0 |
T16 |
3382 |
0 |
0 |
0 |
T17 |
868 |
0 |
0 |
0 |
T18 |
1761 |
0 |
0 |
0 |
T19 |
884 |
0 |
0 |
0 |
T20 |
1788 |
0 |
0 |
0 |
T21 |
960 |
0 |
0 |
0 |
T22 |
780 |
0 |
0 |
0 |
T23 |
0 |
10 |
0 |
0 |
T24 |
0 |
28 |
0 |
0 |
T31 |
0 |
14 |
0 |
0 |
T32 |
0 |
24 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
173139840 |
31158 |
0 |
0 |
T1 |
364052 |
235 |
0 |
0 |
T2 |
120484 |
106 |
0 |
0 |
T3 |
85042 |
30 |
0 |
0 |
T9 |
0 |
458 |
0 |
0 |
T10 |
0 |
34 |
0 |
0 |
T11 |
0 |
862 |
0 |
0 |
T16 |
1690 |
0 |
0 |
0 |
T17 |
1810 |
0 |
0 |
0 |
T18 |
3488 |
0 |
0 |
0 |
T19 |
1768 |
0 |
0 |
0 |
T20 |
931 |
0 |
0 |
0 |
T21 |
1919 |
0 |
0 |
0 |
T22 |
1609 |
0 |
0 |
0 |
T23 |
0 |
10 |
0 |
0 |
T24 |
0 |
28 |
0 |
0 |
T31 |
0 |
14 |
0 |
0 |
T32 |
0 |
24 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
173139840 |
30819 |
0 |
0 |
T1 |
364052 |
235 |
0 |
0 |
T2 |
120484 |
106 |
0 |
0 |
T3 |
85042 |
30 |
0 |
0 |
T9 |
0 |
458 |
0 |
0 |
T10 |
0 |
34 |
0 |
0 |
T11 |
0 |
862 |
0 |
0 |
T16 |
1690 |
0 |
0 |
0 |
T17 |
1810 |
0 |
0 |
0 |
T18 |
3488 |
0 |
0 |
0 |
T19 |
1768 |
0 |
0 |
0 |
T20 |
931 |
0 |
0 |
0 |
T21 |
1919 |
0 |
0 |
0 |
T22 |
1609 |
0 |
0 |
0 |
T23 |
0 |
10 |
0 |
0 |
T24 |
0 |
28 |
0 |
0 |
T31 |
0 |
14 |
0 |
0 |
T32 |
0 |
24 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
252748778 |
31021 |
0 |
0 |
T1 |
170139 |
235 |
0 |
0 |
T2 |
304022 |
106 |
0 |
0 |
T3 |
85042 |
30 |
0 |
0 |
T9 |
0 |
458 |
0 |
0 |
T10 |
0 |
34 |
0 |
0 |
T11 |
0 |
862 |
0 |
0 |
T16 |
3382 |
0 |
0 |
0 |
T17 |
868 |
0 |
0 |
0 |
T18 |
1761 |
0 |
0 |
0 |
T19 |
884 |
0 |
0 |
0 |
T20 |
1788 |
0 |
0 |
0 |
T21 |
960 |
0 |
0 |
0 |
T22 |
780 |
0 |
0 |
0 |
T23 |
0 |
10 |
0 |
0 |
T24 |
0 |
28 |
0 |
0 |
T31 |
0 |
14 |
0 |
0 |
T32 |
0 |
24 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T65,T66,T71 |
1 | 0 | Covered | T65,T66,T71 |
1 | 1 | Covered | T66,T134,T135 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T65,T66,T71 |
1 | 0 | Covered | T66,T134,T135 |
1 | 1 | Covered | T65,T66,T71 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
173139840 |
36 |
0 |
0 |
T65 |
10883 |
2 |
0 |
0 |
T66 |
5712 |
3 |
0 |
0 |
T70 |
10087 |
1 |
0 |
0 |
T71 |
10413 |
1 |
0 |
0 |
T130 |
2954 |
1 |
0 |
0 |
T132 |
6543 |
1 |
0 |
0 |
T133 |
13138 |
1 |
0 |
0 |
T134 |
9418 |
4 |
0 |
0 |
T136 |
5507 |
2 |
0 |
0 |
T137 |
9422 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
494688399 |
36 |
0 |
0 |
T65 |
17126 |
2 |
0 |
0 |
T66 |
13374 |
3 |
0 |
0 |
T70 |
9880 |
1 |
0 |
0 |
T71 |
41650 |
1 |
0 |
0 |
T130 |
11815 |
1 |
0 |
0 |
T132 |
6475 |
1 |
0 |
0 |
T133 |
25225 |
1 |
0 |
0 |
T134 |
22602 |
4 |
0 |
0 |
T136 |
52868 |
2 |
0 |
0 |
T137 |
9422 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T65,T66,T67 |
1 | 0 | Covered | T65,T66,T67 |
1 | 1 | Covered | T66,T136,T134 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T65,T66,T67 |
1 | 0 | Covered | T66,T136,T134 |
1 | 1 | Covered | T65,T66,T67 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
173139840 |
42 |
0 |
0 |
T65 |
10883 |
2 |
0 |
0 |
T66 |
5712 |
3 |
0 |
0 |
T67 |
8400 |
1 |
0 |
0 |
T70 |
10087 |
1 |
0 |
0 |
T71 |
10413 |
3 |
0 |
0 |
T87 |
5412 |
1 |
0 |
0 |
T130 |
2954 |
1 |
0 |
0 |
T132 |
6543 |
1 |
0 |
0 |
T134 |
9418 |
6 |
0 |
0 |
T136 |
5507 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
494688399 |
42 |
0 |
0 |
T65 |
17126 |
2 |
0 |
0 |
T66 |
13374 |
3 |
0 |
0 |
T67 |
16801 |
1 |
0 |
0 |
T70 |
9880 |
1 |
0 |
0 |
T71 |
41650 |
3 |
0 |
0 |
T87 |
5301 |
1 |
0 |
0 |
T130 |
11815 |
1 |
0 |
0 |
T132 |
6475 |
1 |
0 |
0 |
T134 |
22602 |
6 |
0 |
0 |
T136 |
52868 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T68,T65,T66 |
1 | 0 | Covered | T68,T65,T66 |
1 | 1 | Covered | T65,T70,T137 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T68,T65,T66 |
1 | 0 | Covered | T65,T70,T137 |
1 | 1 | Covered | T68,T65,T66 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
173139840 |
35 |
0 |
0 |
T65 |
10883 |
2 |
0 |
0 |
T66 |
5712 |
1 |
0 |
0 |
T67 |
8400 |
2 |
0 |
0 |
T68 |
3609 |
1 |
0 |
0 |
T70 |
10087 |
2 |
0 |
0 |
T85 |
6559 |
1 |
0 |
0 |
T130 |
2954 |
1 |
0 |
0 |
T131 |
15260 |
1 |
0 |
0 |
T132 |
6543 |
1 |
0 |
0 |
T133 |
13138 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
247188951 |
35 |
0 |
0 |
T65 |
7492 |
2 |
0 |
0 |
T66 |
5891 |
1 |
0 |
0 |
T67 |
7753 |
2 |
0 |
0 |
T68 |
6303 |
1 |
0 |
0 |
T70 |
4148 |
2 |
0 |
0 |
T85 |
12744 |
1 |
0 |
0 |
T130 |
5406 |
1 |
0 |
0 |
T131 |
6697 |
1 |
0 |
0 |
T132 |
2803 |
1 |
0 |
0 |
T133 |
11707 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T68,T65,T66 |
1 | 0 | Covered | T68,T65,T66 |
1 | 1 | Covered | T137,T138,T139 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T68,T65,T66 |
1 | 0 | Covered | T137,T138,T139 |
1 | 1 | Covered | T68,T65,T66 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
173139840 |
37 |
0 |
0 |
T65 |
10883 |
1 |
0 |
0 |
T66 |
5712 |
1 |
0 |
0 |
T67 |
8400 |
1 |
0 |
0 |
T68 |
3609 |
2 |
0 |
0 |
T70 |
10087 |
1 |
0 |
0 |
T83 |
7257 |
1 |
0 |
0 |
T131 |
15260 |
1 |
0 |
0 |
T133 |
13138 |
2 |
0 |
0 |
T134 |
9418 |
1 |
0 |
0 |
T136 |
5507 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
247188951 |
37 |
0 |
0 |
T65 |
7492 |
1 |
0 |
0 |
T66 |
5891 |
1 |
0 |
0 |
T67 |
7753 |
1 |
0 |
0 |
T68 |
6303 |
2 |
0 |
0 |
T70 |
4148 |
1 |
0 |
0 |
T83 |
6945 |
1 |
0 |
0 |
T131 |
6697 |
1 |
0 |
0 |
T133 |
11707 |
2 |
0 |
0 |
T134 |
10479 |
1 |
0 |
0 |
T136 |
25510 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T66,T71,T70 |
1 | 0 | Covered | T66,T71,T70 |
1 | 1 | Covered | T140 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T66,T71,T70 |
1 | 0 | Covered | T140 |
1 | 1 | Covered | T66,T71,T70 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
173139840 |
27 |
0 |
0 |
T66 |
5712 |
1 |
0 |
0 |
T70 |
10087 |
1 |
0 |
0 |
T71 |
10413 |
2 |
0 |
0 |
T130 |
2954 |
1 |
0 |
0 |
T131 |
15260 |
2 |
0 |
0 |
T135 |
5267 |
2 |
0 |
0 |
T136 |
5507 |
2 |
0 |
0 |
T141 |
9581 |
1 |
0 |
0 |
T142 |
5391 |
1 |
0 |
0 |
T143 |
13241 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123593830 |
27 |
0 |
0 |
T66 |
2946 |
1 |
0 |
0 |
T70 |
2079 |
1 |
0 |
0 |
T71 |
10039 |
2 |
0 |
0 |
T130 |
2704 |
1 |
0 |
0 |
T131 |
3348 |
2 |
0 |
0 |
T135 |
1168 |
2 |
0 |
0 |
T136 |
12755 |
2 |
0 |
0 |
T141 |
2029 |
1 |
0 |
0 |
T142 |
1139 |
1 |
0 |
0 |
T143 |
2741 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T68,T66,T70 |
1 | 0 | Covered | T68,T66,T70 |
1 | 1 | Covered | T135,T144 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T68,T66,T70 |
1 | 0 | Covered | T135,T144 |
1 | 1 | Covered | T68,T66,T70 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
173139840 |
28 |
0 |
0 |
T66 |
5712 |
1 |
0 |
0 |
T68 |
3609 |
1 |
0 |
0 |
T70 |
10087 |
1 |
0 |
0 |
T131 |
15260 |
4 |
0 |
0 |
T135 |
5267 |
3 |
0 |
0 |
T136 |
5507 |
1 |
0 |
0 |
T142 |
5391 |
1 |
0 |
0 |
T143 |
13241 |
1 |
0 |
0 |
T145 |
7321 |
1 |
0 |
0 |
T146 |
9558 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123593830 |
28 |
0 |
0 |
T66 |
2946 |
1 |
0 |
0 |
T68 |
3152 |
1 |
0 |
0 |
T70 |
2079 |
1 |
0 |
0 |
T131 |
3348 |
4 |
0 |
0 |
T135 |
1168 |
3 |
0 |
0 |
T136 |
12755 |
1 |
0 |
0 |
T142 |
1139 |
1 |
0 |
0 |
T143 |
2741 |
1 |
0 |
0 |
T145 |
3242 |
1 |
0 |
0 |
T146 |
2930 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T65,T66,T67 |
1 | 0 | Covered | T65,T66,T67 |
1 | 1 | Covered | T67,T147,T143 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T65,T66,T67 |
1 | 0 | Covered | T67,T147,T143 |
1 | 1 | Covered | T65,T66,T67 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
173139840 |
37 |
0 |
0 |
T65 |
10883 |
2 |
0 |
0 |
T66 |
5712 |
1 |
0 |
0 |
T67 |
8400 |
3 |
0 |
0 |
T70 |
10087 |
2 |
0 |
0 |
T85 |
6559 |
1 |
0 |
0 |
T133 |
13138 |
1 |
0 |
0 |
T134 |
9418 |
1 |
0 |
0 |
T136 |
5507 |
1 |
0 |
0 |
T137 |
9422 |
2 |
0 |
0 |
T145 |
7321 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526740827 |
37 |
0 |
0 |
T65 |
17841 |
2 |
0 |
0 |
T66 |
13932 |
1 |
0 |
0 |
T67 |
17502 |
3 |
0 |
0 |
T70 |
10292 |
2 |
0 |
0 |
T85 |
27329 |
1 |
0 |
0 |
T133 |
26278 |
1 |
0 |
0 |
T134 |
23545 |
1 |
0 |
0 |
T136 |
55072 |
1 |
0 |
0 |
T137 |
9815 |
2 |
0 |
0 |
T145 |
14942 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T65,T67,T70 |
1 | 0 | Covered | T65,T67,T70 |
1 | 1 | Covered | T67,T131,T137 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T65,T67,T70 |
1 | 0 | Covered | T67,T131,T137 |
1 | 1 | Covered | T65,T67,T70 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
173139840 |
37 |
0 |
0 |
T65 |
10883 |
3 |
0 |
0 |
T67 |
8400 |
2 |
0 |
0 |
T70 |
10087 |
1 |
0 |
0 |
T85 |
6559 |
1 |
0 |
0 |
T131 |
15260 |
2 |
0 |
0 |
T133 |
13138 |
1 |
0 |
0 |
T134 |
9418 |
3 |
0 |
0 |
T136 |
5507 |
1 |
0 |
0 |
T137 |
9422 |
2 |
0 |
0 |
T148 |
4192 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526740827 |
37 |
0 |
0 |
T65 |
17841 |
3 |
0 |
0 |
T67 |
17502 |
2 |
0 |
0 |
T70 |
10292 |
1 |
0 |
0 |
T85 |
27329 |
1 |
0 |
0 |
T131 |
16064 |
2 |
0 |
0 |
T133 |
26278 |
1 |
0 |
0 |
T134 |
23545 |
3 |
0 |
0 |
T136 |
55072 |
1 |
0 |
0 |
T137 |
9815 |
2 |
0 |
0 |
T148 |
17467 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T65,T69,T66 |
1 | 0 | Covered | T65,T69,T66 |
1 | 1 | Covered | T65,T69,T131 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T65,T69,T66 |
1 | 0 | Covered | T65,T69,T131 |
1 | 1 | Covered | T65,T69,T66 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
173139840 |
35 |
0 |
0 |
T65 |
10883 |
3 |
0 |
0 |
T66 |
5712 |
1 |
0 |
0 |
T67 |
8400 |
1 |
0 |
0 |
T69 |
4334 |
2 |
0 |
0 |
T130 |
2954 |
1 |
0 |
0 |
T131 |
15260 |
2 |
0 |
0 |
T134 |
9418 |
1 |
0 |
0 |
T136 |
5507 |
2 |
0 |
0 |
T137 |
9422 |
3 |
0 |
0 |
T145 |
7321 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
252748778 |
35 |
0 |
0 |
T65 |
8563 |
3 |
0 |
0 |
T66 |
6687 |
1 |
0 |
0 |
T67 |
8400 |
1 |
0 |
0 |
T69 |
34679 |
2 |
0 |
0 |
T130 |
5908 |
1 |
0 |
0 |
T131 |
7711 |
2 |
0 |
0 |
T134 |
11302 |
1 |
0 |
0 |
T136 |
26435 |
2 |
0 |
0 |
T137 |
4711 |
3 |
0 |
0 |
T145 |
7172 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T65,T69,T66 |
1 | 0 | Covered | T65,T69,T66 |
1 | 1 | Covered | T65,T66,T131 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T65,T69,T66 |
1 | 0 | Covered | T65,T66,T131 |
1 | 1 | Covered | T65,T69,T66 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
173139840 |
29 |
0 |
0 |
T65 |
10883 |
2 |
0 |
0 |
T66 |
5712 |
2 |
0 |
0 |
T67 |
8400 |
1 |
0 |
0 |
T69 |
4334 |
1 |
0 |
0 |
T71 |
10413 |
1 |
0 |
0 |
T131 |
15260 |
2 |
0 |
0 |
T134 |
9418 |
1 |
0 |
0 |
T136 |
5507 |
1 |
0 |
0 |
T137 |
9422 |
1 |
0 |
0 |
T145 |
7321 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
252748778 |
29 |
0 |
0 |
T65 |
8563 |
2 |
0 |
0 |
T66 |
6687 |
2 |
0 |
0 |
T67 |
8400 |
1 |
0 |
0 |
T69 |
34679 |
1 |
0 |
0 |
T71 |
20826 |
1 |
0 |
0 |
T131 |
7711 |
2 |
0 |
0 |
T134 |
11302 |
1 |
0 |
0 |
T136 |
26435 |
1 |
0 |
0 |
T137 |
4711 |
1 |
0 |
0 |
T145 |
7172 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
492120848 |
93505 |
0 |
0 |
T1 |
329895 |
987 |
0 |
0 |
T2 |
527376 |
377 |
0 |
0 |
T3 |
170075 |
68 |
0 |
0 |
T9 |
0 |
1760 |
0 |
0 |
T10 |
0 |
97 |
0 |
0 |
T11 |
0 |
3495 |
0 |
0 |
T16 |
6765 |
0 |
0 |
0 |
T17 |
1738 |
0 |
0 |
0 |
T18 |
3523 |
0 |
0 |
0 |
T19 |
1768 |
0 |
0 |
0 |
T20 |
3577 |
0 |
0 |
0 |
T21 |
1919 |
0 |
0 |
0 |
T22 |
1560 |
0 |
0 |
0 |
T23 |
0 |
30 |
0 |
0 |
T24 |
0 |
142 |
0 |
0 |
T31 |
0 |
89 |
0 |
0 |
T32 |
0 |
134 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
18398752 |
92844 |
0 |
0 |
T1 |
161200 |
987 |
0 |
0 |
T2 |
2020 |
377 |
0 |
0 |
T3 |
366 |
68 |
0 |
0 |
T9 |
0 |
1761 |
0 |
0 |
T10 |
0 |
97 |
0 |
0 |
T11 |
0 |
3496 |
0 |
0 |
T16 |
493 |
0 |
0 |
0 |
T17 |
126 |
0 |
0 |
0 |
T18 |
256 |
0 |
0 |
0 |
T19 |
128 |
0 |
0 |
0 |
T20 |
260 |
0 |
0 |
0 |
T21 |
139 |
0 |
0 |
0 |
T22 |
113 |
0 |
0 |
0 |
T23 |
0 |
30 |
0 |
0 |
T24 |
0 |
142 |
0 |
0 |
T31 |
0 |
89 |
0 |
0 |
T32 |
0 |
134 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
245951634 |
93306 |
0 |
0 |
T1 |
164774 |
987 |
0 |
0 |
T2 |
263417 |
377 |
0 |
0 |
T3 |
85005 |
68 |
0 |
0 |
T9 |
0 |
1743 |
0 |
0 |
T10 |
0 |
97 |
0 |
0 |
T11 |
0 |
3485 |
0 |
0 |
T16 |
3820 |
0 |
0 |
0 |
T17 |
865 |
0 |
0 |
0 |
T18 |
1695 |
0 |
0 |
0 |
T19 |
881 |
0 |
0 |
0 |
T20 |
1768 |
0 |
0 |
0 |
T21 |
998 |
0 |
0 |
0 |
T22 |
768 |
0 |
0 |
0 |
T23 |
0 |
30 |
0 |
0 |
T24 |
0 |
142 |
0 |
0 |
T31 |
0 |
89 |
0 |
0 |
T32 |
0 |
134 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
18398752 |
92646 |
0 |
0 |
T1 |
161200 |
987 |
0 |
0 |
T2 |
2020 |
377 |
0 |
0 |
T3 |
366 |
68 |
0 |
0 |
T9 |
0 |
1744 |
0 |
0 |
T10 |
0 |
97 |
0 |
0 |
T11 |
0 |
3486 |
0 |
0 |
T16 |
493 |
0 |
0 |
0 |
T17 |
126 |
0 |
0 |
0 |
T18 |
256 |
0 |
0 |
0 |
T19 |
128 |
0 |
0 |
0 |
T20 |
260 |
0 |
0 |
0 |
T21 |
139 |
0 |
0 |
0 |
T22 |
113 |
0 |
0 |
0 |
T23 |
0 |
30 |
0 |
0 |
T24 |
0 |
142 |
0 |
0 |
T31 |
0 |
89 |
0 |
0 |
T32 |
0 |
134 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
122975165 |
92897 |
0 |
0 |
T1 |
823867 |
987 |
0 |
0 |
T2 |
131709 |
377 |
0 |
0 |
T3 |
42502 |
68 |
0 |
0 |
T9 |
0 |
1714 |
0 |
0 |
T10 |
0 |
97 |
0 |
0 |
T11 |
0 |
3479 |
0 |
0 |
T16 |
1910 |
0 |
0 |
0 |
T17 |
432 |
0 |
0 |
0 |
T18 |
847 |
0 |
0 |
0 |
T19 |
440 |
0 |
0 |
0 |
T20 |
884 |
0 |
0 |
0 |
T21 |
498 |
0 |
0 |
0 |
T22 |
384 |
0 |
0 |
0 |
T23 |
0 |
30 |
0 |
0 |
T24 |
0 |
142 |
0 |
0 |
T31 |
0 |
89 |
0 |
0 |
T32 |
0 |
134 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
18398752 |
92241 |
0 |
0 |
T1 |
161200 |
987 |
0 |
0 |
T2 |
2020 |
377 |
0 |
0 |
T3 |
366 |
68 |
0 |
0 |
T9 |
0 |
1715 |
0 |
0 |
T10 |
0 |
97 |
0 |
0 |
T11 |
0 |
3480 |
0 |
0 |
T16 |
493 |
0 |
0 |
0 |
T17 |
126 |
0 |
0 |
0 |
T18 |
256 |
0 |
0 |
0 |
T19 |
128 |
0 |
0 |
0 |
T20 |
260 |
0 |
0 |
0 |
T21 |
139 |
0 |
0 |
0 |
T22 |
113 |
0 |
0 |
0 |
T23 |
0 |
30 |
0 |
0 |
T24 |
0 |
142 |
0 |
0 |
T31 |
0 |
89 |
0 |
0 |
T32 |
0 |
134 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
524066189 |
114879 |
0 |
0 |
T1 |
357452 |
1263 |
0 |
0 |
T2 |
663368 |
605 |
0 |
0 |
T3 |
177167 |
68 |
0 |
0 |
T9 |
0 |
2058 |
0 |
0 |
T10 |
0 |
97 |
0 |
0 |
T11 |
0 |
4418 |
0 |
0 |
T16 |
7047 |
0 |
0 |
0 |
T17 |
1810 |
0 |
0 |
0 |
T18 |
3671 |
0 |
0 |
0 |
T19 |
1843 |
0 |
0 |
0 |
T20 |
3726 |
0 |
0 |
0 |
T21 |
1999 |
0 |
0 |
0 |
T22 |
1625 |
0 |
0 |
0 |
T23 |
0 |
78 |
0 |
0 |
T24 |
0 |
226 |
0 |
0 |
T31 |
0 |
77 |
0 |
0 |
T32 |
0 |
170 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
18439661 |
114139 |
0 |
0 |
T1 |
161476 |
1263 |
0 |
0 |
T2 |
2248 |
605 |
0 |
0 |
T3 |
366 |
68 |
0 |
0 |
T9 |
0 |
2058 |
0 |
0 |
T10 |
0 |
97 |
0 |
0 |
T11 |
0 |
4418 |
0 |
0 |
T16 |
493 |
0 |
0 |
0 |
T17 |
126 |
0 |
0 |
0 |
T18 |
256 |
0 |
0 |
0 |
T19 |
128 |
0 |
0 |
0 |
T20 |
260 |
0 |
0 |
0 |
T21 |
139 |
0 |
0 |
0 |
T22 |
113 |
0 |
0 |
0 |
T23 |
0 |
78 |
0 |
0 |
T24 |
0 |
226 |
0 |
0 |
T31 |
0 |
77 |
0 |
0 |
T32 |
0 |
170 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
251464983 |
113710 |
0 |
0 |
T1 |
170139 |
1203 |
0 |
0 |
T2 |
304022 |
545 |
0 |
0 |
T3 |
85042 |
68 |
0 |
0 |
T9 |
0 |
2105 |
0 |
0 |
T10 |
0 |
91 |
0 |
0 |
T11 |
0 |
4167 |
0 |
0 |
T16 |
3382 |
0 |
0 |
0 |
T17 |
868 |
0 |
0 |
0 |
T18 |
1761 |
0 |
0 |
0 |
T19 |
884 |
0 |
0 |
0 |
T20 |
1788 |
0 |
0 |
0 |
T21 |
960 |
0 |
0 |
0 |
T22 |
780 |
0 |
0 |
0 |
T23 |
0 |
66 |
0 |
0 |
T24 |
0 |
166 |
0 |
0 |
T31 |
0 |
113 |
0 |
0 |
T32 |
0 |
170 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
18635050 |
113713 |
0 |
0 |
T1 |
161416 |
1203 |
0 |
0 |
T2 |
2188 |
545 |
0 |
0 |
T3 |
366 |
68 |
0 |
0 |
T9 |
0 |
2105 |
0 |
0 |
T10 |
0 |
91 |
0 |
0 |
T11 |
0 |
4167 |
0 |
0 |
T16 |
493 |
0 |
0 |
0 |
T17 |
126 |
0 |
0 |
0 |
T18 |
256 |
0 |
0 |
0 |
T19 |
128 |
0 |
0 |
0 |
T20 |
260 |
0 |
0 |
0 |
T21 |
139 |
0 |
0 |
0 |
T22 |
113 |
0 |
0 |
0 |
T23 |
0 |
66 |
0 |
0 |
T24 |
0 |
166 |
0 |
0 |
T31 |
0 |
113 |
0 |
0 |
T32 |
0 |
170 |
0 |
0 |