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Module Instance : tb.dut.u_reg.u_extclk_ctrl_regwen.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_extclk_ctrl_regwen


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_extclk_ctrl_sel.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_extclk_ctrl_sel


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_extclk_ctrl_hi_speed_sel.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_extclk_ctrl_hi_speed_sel


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_jitter_regwen.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_jitter_regwen


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_jitter_enable.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_jitter_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_clk_enables_clk_io_div4_peri_en.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_enables_clk_io_div4_peri_en


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_clk_enables_clk_io_div2_peri_en.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_enables_clk_io_div2_peri_en


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_clk_enables_clk_io_peri_en.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_enables_clk_io_peri_en


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_clk_enables_clk_usb_peri_en.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_enables_clk_usb_peri_en


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_clk_hints_clk_main_aes_hint.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_hints_clk_main_aes_hint


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_clk_hints_clk_main_hmac_hint.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_hints_clk_main_hmac_hint


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_clk_hints_clk_main_kmac_hint.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_hints_clk_main_kmac_hint


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_clk_hints_clk_main_otbn_hint.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_hints_clk_main_otbn_hint


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_clk_hints_status_clk_main_aes_val.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.24 85.71 100.00 100.00 u_clk_hints_status_clk_main_aes_val


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_clk_hints_status_clk_main_hmac_val.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.24 85.71 100.00 100.00 u_clk_hints_status_clk_main_hmac_val


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_clk_hints_status_clk_main_kmac_val.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.24 85.71 100.00 100.00 u_clk_hints_status_clk_main_kmac_val


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_clk_hints_status_clk_main_otbn_val.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.24 85.71 100.00 100.00 u_clk_hints_status_clk_main_otbn_val


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_measure_ctrl_regwen.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_measure_ctrl_regwen


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_io_meas_ctrl_en


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.04 100.00 96.15 100.00 100.00 u_io_meas_ctrl_shadowed_hi


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.staged_reg.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 staged_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_reg.u_extclk_ctrl_regwen.wr_en_data_arb
tb.dut.u_reg.u_extclk_ctrl_sel.wr_en_data_arb
tb.dut.u_reg.u_extclk_ctrl_hi_speed_sel.wr_en_data_arb
tb.dut.u_reg.u_jitter_regwen.wr_en_data_arb
tb.dut.u_reg.u_jitter_enable.wr_en_data_arb
tb.dut.u_reg.u_clk_enables_clk_io_div4_peri_en.wr_en_data_arb
tb.dut.u_reg.u_clk_enables_clk_io_div2_peri_en.wr_en_data_arb
tb.dut.u_reg.u_clk_enables_clk_io_peri_en.wr_en_data_arb
tb.dut.u_reg.u_clk_enables_clk_usb_peri_en.wr_en_data_arb
tb.dut.u_reg.u_clk_hints_clk_main_aes_hint.wr_en_data_arb
tb.dut.u_reg.u_clk_hints_clk_main_hmac_hint.wr_en_data_arb
tb.dut.u_reg.u_clk_hints_clk_main_kmac_hint.wr_en_data_arb
tb.dut.u_reg.u_clk_hints_clk_main_otbn_hint.wr_en_data_arb
tb.dut.u_reg.u_clk_hints_status_clk_main_aes_val.wr_en_data_arb
tb.dut.u_reg.u_clk_hints_status_clk_main_hmac_val.wr_en_data_arb
tb.dut.u_reg.u_clk_hints_status_clk_main_kmac_val.wr_en_data_arb
tb.dut.u_reg.u_clk_hints_status_clk_main_otbn_val.wr_en_data_arb
tb.dut.u_reg.u_measure_ctrl_regwen.wr_en_data_arb
tb.dut.u_reg.u_io_meas_ctrl_en.wr_en_data_arb
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.wr_en_data_arb
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.staged_reg.wr_en_data_arb
Line Coverage for Instance : tb.dut.u_reg.u_extclk_ctrl_regwen.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
113 1 1
135 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_extclk_ctrl_regwen.wr_en_data_arb
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T1
01Unreachable
10CoveredT1,T16,T17 

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT108,T76,T109
10CoveredT108,T76,T109
11CoveredT4,T5,T1 

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT4,T5,T1
1Unreachable 

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT1,T16,T17
Line Coverage for Instance : tb.dut.u_reg.u_extclk_ctrl_sel.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_extclk_ctrl_sel.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T1
01Unreachable
10CoveredT1,T16,T17 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT1,T16,T17 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT1,T16,T17
Branch Coverage for Instance : tb.dut.u_reg.u_extclk_ctrl_sel.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T1,T16,T17
0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.u_reg.u_extclk_ctrl_hi_speed_sel.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_extclk_ctrl_hi_speed_sel.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T1
01Unreachable
10CoveredT1,T16,T17 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT1,T16,T17 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT1,T16,T17
Branch Coverage for Instance : tb.dut.u_reg.u_extclk_ctrl_hi_speed_sel.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T1,T16,T17
0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.u_reg.u_jitter_regwen.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
113 1 1
135 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_jitter_regwen.wr_en_data_arb
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T1
01Unreachable
10CoveredT68,T69,T113 

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT68,T69,T113
10CoveredT68,T69,T113
11CoveredT4,T5,T1 

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT4,T5,T1
1Unreachable 

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT68,T69,T113
Line Coverage for Instance : tb.dut.u_reg.u_jitter_enable.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_jitter_enable.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T1
01Unreachable
10CoveredT1,T2,T9 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT1,T2,T9 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT1,T2,T9
Branch Coverage for Instance : tb.dut.u_reg.u_jitter_enable.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T9
0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.u_reg.u_clk_enables_clk_io_div4_peri_en.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_clk_enables_clk_io_div4_peri_en.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T1
01Unreachable
10CoveredT4,T1,T2 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT4,T1,T2 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT4,T1,T2
Branch Coverage for Instance : tb.dut.u_reg.u_clk_enables_clk_io_div4_peri_en.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T4,T1,T2
0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.u_reg.u_clk_enables_clk_io_div2_peri_en.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_clk_enables_clk_io_div2_peri_en.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T1
01Unreachable
10CoveredT4,T1,T2 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT4,T1,T2 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT4,T1,T2
Branch Coverage for Instance : tb.dut.u_reg.u_clk_enables_clk_io_div2_peri_en.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T4,T1,T2
0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.u_reg.u_clk_enables_clk_io_peri_en.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_clk_enables_clk_io_peri_en.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T1
01Unreachable
10CoveredT4,T1,T2 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT4,T1,T2 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT4,T1,T2
Branch Coverage for Instance : tb.dut.u_reg.u_clk_enables_clk_io_peri_en.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T4,T1,T2
0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.u_reg.u_clk_enables_clk_usb_peri_en.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_clk_enables_clk_usb_peri_en.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T1
01Unreachable
10CoveredT4,T1,T2 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT4,T1,T2 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT4,T1,T2
Branch Coverage for Instance : tb.dut.u_reg.u_clk_enables_clk_usb_peri_en.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T4,T1,T2
0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.u_reg.u_clk_hints_clk_main_aes_hint.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_clk_hints_clk_main_aes_hint.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T1
01Unreachable
10CoveredT5,T1,T18 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT5,T1,T18 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT5,T1,T18
Branch Coverage for Instance : tb.dut.u_reg.u_clk_hints_clk_main_aes_hint.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T5,T1,T18
0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.u_reg.u_clk_hints_clk_main_hmac_hint.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_clk_hints_clk_main_hmac_hint.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T1
01Unreachable
10CoveredT5,T1,T18 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT5,T1,T18 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT5,T1,T18
Branch Coverage for Instance : tb.dut.u_reg.u_clk_hints_clk_main_hmac_hint.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T5,T1,T18
0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.u_reg.u_clk_hints_clk_main_kmac_hint.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_clk_hints_clk_main_kmac_hint.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T1
01Unreachable
10CoveredT5,T1,T18 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT5,T1,T18 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT5,T1,T18
Branch Coverage for Instance : tb.dut.u_reg.u_clk_hints_clk_main_kmac_hint.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T5,T1,T18
0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.u_reg.u_clk_hints_clk_main_otbn_hint.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_clk_hints_clk_main_otbn_hint.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T1
01Unreachable
10CoveredT5,T1,T18 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT5,T1,T18 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT5,T1,T18
Branch Coverage for Instance : tb.dut.u_reg.u_clk_hints_clk_main_otbn_hint.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T5,T1,T18
0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.u_reg.u_clk_hints_status_clk_main_aes_val.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN43100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
43 0 1
44 1 1
51 unreachable
52 unreachable
53 unreachable

Line Coverage for Instance : tb.dut.u_reg.u_clk_hints_status_clk_main_hmac_val.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN43100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
43 0 1
44 1 1
51 unreachable
52 unreachable
53 unreachable

Line Coverage for Instance : tb.dut.u_reg.u_clk_hints_status_clk_main_kmac_val.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN43100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
43 0 1
44 1 1
51 unreachable
52 unreachable
53 unreachable

Line Coverage for Instance : tb.dut.u_reg.u_clk_hints_status_clk_main_otbn_val.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN43100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
43 0 1
44 1 1
51 unreachable
52 unreachable
53 unreachable

Line Coverage for Instance : tb.dut.u_reg.u_measure_ctrl_regwen.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
113 1 1
135 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_measure_ctrl_regwen.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT4,T5,T1
10CoveredT1,T2,T3 

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT1,T2,T9
10CoveredT1,T2,T3
11CoveredT4,T5,T1 

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT4,T5,T1 

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en.wr_en_data_arb
TotalCoveredPercent
Conditions77100.00
Logical77100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT1,T2,T3
10CoveredT1,T2,T3 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT1,T2,T3 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T1
01Unreachable
10CoveredT1,T2,T3 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT1,T2,T3 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.staged_reg.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.staged_reg.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T1
01Unreachable
10CoveredT1,T2,T3 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT1,T2,T3 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.staged_reg.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T5,T1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%