Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	173139840	6203975	0	0
clk_enables_rd_A	173139840	23818	0	0
clk_hints_rd_A	173139840	20713	0	0
extclk_ctrl_rd_A	173139840	26000	0	0
extclk_ctrl_regwen_rd_A	173139840	19532	0	0
jitter_enable_rd_A	173139840	28389	0	0
jitter_regwen_rd_A	173139840	21964	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173139840	6203975	0	0
T1	364052	179472	0	0
T2	120484	0	0	0
T3	85042	0	0	0
T9	0	112857	0	0
T11	0	323923	0	0
T12	0	235792	0	0
T13	0	85428	0	0
T14	0	112363	0	0
T16	1690	0	0	0
T17	1810	0	0	0
T18	3488	0	0	0
T19	1768	0	0	0
T20	931	0	0	0
T21	1919	0	0	0
T22	1609	0	0	0
T25	0	93991	0	0
T73	0	129641	0	0
T74	0	187417	0	0
T75	0	27323	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173139840	23818	0	0
T43	18652	0	0	0
T46	48882	0	0	0
T47	502959	0	0	0
T48	972	0	0	0
T49	1431	0	0	0
T50	774	0	0	0
T51	2863	0	0	0
T52	1200	0	0	0
T149	2491	1	0	0
T150	0	2	0	0
T151	0	1844	0	0
T152	0	9	0	0
T153	0	19	0	0
T154	0	15	0	0
T155	0	4	0	0
T156	0	6	0	0
T157	0	1	0	0
T158	0	6	0	0
T159	1306	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173139840	20713	0	0
T129	19962	0	0	0
T149	0	1	0	0
T151	0	1741	0	0
T152	0	5	0	0
T153	0	14	0	0
T154	0	5	0	0
T156	0	3	0	0
T157	0	5	0	0
T158	0	5	0	0
T160	2110	1	0	0
T161	0	6	0	0
T162	70621	0	0	0
T163	1244	0	0	0
T164	1101	0	0	0
T165	1435	0	0	0
T166	881	0	0	0
T167	2760	0	0	0
T168	2100	0	0	0
T169	1505	0	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173139840	26000	0	0
T9	317750	0	0	0
T23	61704	0	0	0
T24	85262	0	0	0
T27	915	8	0	0
T28	1457	0	0	0
T29	1411	0	0	0
T30	1756	0	0	0
T58	0	72	0	0
T64	0	10	0	0
T72	2395	33	0	0
T109	0	10	0	0
T120	1635	0	0	0
T121	1510	0	0	0
T170	0	43	0	0
T171	0	3	0	0
T172	0	59	0	0
T173	0	48	0	0
T174	0	19	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173139840	19532	0	0
T37	184692	0	0	0
T56	9485	0	0	0
T78	58772	0	0	0
T109	4662	8	0	0
T151	0	1593	0	0
T175	0	19	0	0
T176	0	63	0	0
T177	0	16	0	0
T178	0	59	0	0
T179	0	24	0	0
T180	0	5042	0	0
T181	0	4	0	0
T182	0	1186	0	0
T183	1522	0	0	0
T184	1726	0	0	0
T185	789	0	0	0
T186	17900	0	0	0
T187	2499	0	0	0
T188	1746	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173139840	28389	0	0
T129	19962	0	0	0
T149	0	105	0	0
T150	0	99	0	0
T151	0	2408	0	0
T152	0	450	0	0
T153	0	530	0	0
T154	0	233	0	0
T155	0	68	0	0
T156	0	237	0	0
T160	2110	113	0	0
T162	70621	0	0	0
T163	1244	0	0	0
T164	1101	0	0	0
T165	1435	0	0	0
T166	881	0	0	0
T167	2760	0	0	0
T168	2100	0	0	0
T169	1505	0	0	0
T189	0	84	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173139840	21964	0	0
T7	108851	0	0	0
T65	0	48	0	0
T83	0	96	0	0
T85	0	90	0	0
T151	182093	1886	0	0
T152	161283	0	0	0
T180	0	5654	0	0
T182	0	1565	0	0
T190	0	5784	0	0
T191	0	5188	0	0
T192	0	27	0	0
T193	0	16	0	0
T194	2322	0	0	0
T195	1512	0	0	0
T196	12113	0	0	0
T197	65362	0	0	0
T198	2165	0	0	0
T199	1414	0	0	0
T200	301725	0	0	0