Module Definition
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Module : clkmgr_div_sva_if
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.clkmgr_div2_sva_if 100.00 100.00 100.00 100.00
tb.dut.clkmgr_div4_sva_if 100.00 100.00 100.00 100.00



Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Module : clkmgr_div_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT4,T1,T16
10CoveredT1,T16,T17
11CoveredT1,T16,T17

Assert Coverage for Module : clkmgr_div_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div2.Div2Stepped_A 492121301 4586 0 0
g_div2.Div2Whole_A 492121301 5389 0 0
g_div4.Div4Stepped_A 245952037 4491 0 0
g_div4.Div4Whole_A 245952037 5132 0 0


g_div2.Div2Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 492121301 4586 0 0
T1 329895 14 0 0
T2 527377 0 0 0
T3 170076 0 0 0
T9 0 65 0 0
T16 6765 9 0 0
T17 1739 1 0 0
T18 3524 0 0 0
T19 1769 2 0 0
T20 3578 0 0 0
T21 1920 6 0 0
T22 1560 0 0 0
T27 0 1 0 0
T29 0 6 0 0
T30 0 9 0 0
T120 0 1 0 0

g_div2.Div2Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 492121301 5389 0 0
T1 329895 23 0 0
T2 527377 0 0 0
T3 170076 0 0 0
T9 0 71 0 0
T16 6765 10 0 0
T17 1739 7 0 0
T18 3524 0 0 0
T19 1769 5 0 0
T20 3578 1 0 0
T21 1920 8 0 0
T22 1560 0 0 0
T27 0 1 0 0
T29 0 6 0 0
T30 0 10 0 0

g_div4.Div4Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 245952037 4491 0 0
T1 164774 11 0 0
T2 263417 0 0 0
T3 85005 0 0 0
T9 0 65 0 0
T16 3820 9 0 0
T17 866 1 0 0
T18 1695 0 0 0
T19 881 2 0 0
T20 1768 0 0 0
T21 998 6 0 0
T22 768 0 0 0
T27 0 1 0 0
T29 0 6 0 0
T30 0 9 0 0
T120 0 1 0 0

g_div4.Div4Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 245952037 5132 0 0
T1 164774 20 0 0
T2 263417 0 0 0
T3 85005 0 0 0
T9 0 71 0 0
T16 3820 10 0 0
T17 866 6 0 0
T18 1695 0 0 0
T19 881 5 0 0
T20 1768 1 0 0
T21 998 8 0 0
T22 768 0 0 0
T27 0 1 0 0
T29 0 5 0 0
T30 0 10 0 0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT4,T1,T16
10CoveredT1,T16,T17
11CoveredT1,T16,T17

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div2.Div2Stepped_A 492121301 4586 0 0
g_div2.Div2Whole_A 492121301 5389 0 0


g_div2.Div2Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 492121301 4586 0 0
T1 329895 14 0 0
T2 527377 0 0 0
T3 170076 0 0 0
T9 0 65 0 0
T16 6765 9 0 0
T17 1739 1 0 0
T18 3524 0 0 0
T19 1769 2 0 0
T20 3578 0 0 0
T21 1920 6 0 0
T22 1560 0 0 0
T27 0 1 0 0
T29 0 6 0 0
T30 0 9 0 0
T120 0 1 0 0

g_div2.Div2Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 492121301 5389 0 0
T1 329895 23 0 0
T2 527377 0 0 0
T3 170076 0 0 0
T9 0 71 0 0
T16 6765 10 0 0
T17 1739 7 0 0
T18 3524 0 0 0
T19 1769 5 0 0
T20 3578 1 0 0
T21 1920 8 0 0
T22 1560 0 0 0
T27 0 1 0 0
T29 0 6 0 0
T30 0 10 0 0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT4,T1,T16
10CoveredT1,T16,T17
11CoveredT1,T16,T17

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div4.Div4Stepped_A 245952037 4491 0 0
g_div4.Div4Whole_A 245952037 5132 0 0


g_div4.Div4Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 245952037 4491 0 0
T1 164774 11 0 0
T2 263417 0 0 0
T3 85005 0 0 0
T9 0 65 0 0
T16 3820 9 0 0
T17 866 1 0 0
T18 1695 0 0 0
T19 881 2 0 0
T20 1768 0 0 0
T21 998 6 0 0
T22 768 0 0 0
T27 0 1 0 0
T29 0 6 0 0
T30 0 9 0 0
T120 0 1 0 0

g_div4.Div4Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 245952037 5132 0 0
T1 164774 20 0 0
T2 263417 0 0 0
T3 85005 0 0 0
T9 0 71 0 0
T16 3820 10 0 0
T17 866 6 0 0
T18 1695 0 0 0
T19 881 5 0 0
T20 1768 1 0 0
T21 998 8 0 0
T22 768 0 0 0
T27 0 1 0 0
T29 0 5 0 0
T30 0 10 0 0

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