Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	516742560	374	0	0
StatusRise_A	516742560	374	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516742560	374	0	0
T12	1453434	0	0	0
T13	729249	0	0	0
T34	2546	0	0	0
T38	1522	1	0	0
T39	3528	9	0	0
T40	4596	6	0	0
T41	4134	2	0	0
T42	0	5	0	0
T62	0	6	0	0
T89	0	9	0	0
T108	16971	0	0	0
T185	0	8	0	0
T201	0	3	0	0
T202	0	6	0	0
T203	0	10	0	0
T204	0	5	0	0
T205	3513	0	0	0
T206	4731	0	0	0
T207	40194	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516742560	374	0	0
T12	1453434	0	0	0
T13	729249	0	0	0
T34	2546	0	0	0
T38	1522	1	0	0
T39	3528	9	0	0
T40	4596	6	0	0
T41	4134	2	0	0
T42	0	5	0	0
T62	0	6	0	0
T89	0	9	0	0
T108	16971	0	0	0
T185	0	8	0	0
T201	0	3	0	0
T202	0	6	0	0
T203	0	10	0	0
T204	0	5	0	0
T205	3513	0	0	0
T206	4731	0	0	0
T207	40194	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	172247520	125	0	0
StatusRise_A	172247520	125	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172247520	125	0	0
T12	484478	0	0	0
T13	243083	0	0	0
T34	1273	0	0	0
T39	1176	3	0	0
T40	1532	2	0	0
T41	1378	0	0	0
T42	0	1	0	0
T62	0	2	0	0
T89	0	4	0	0
T108	5657	0	0	0
T185	0	2	0	0
T201	0	1	0	0
T202	0	1	0	0
T203	0	2	0	0
T204	0	5	0	0
T205	1171	0	0	0
T206	1577	0	0	0
T207	13398	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172247520	125	0	0
T12	484478	0	0	0
T13	243083	0	0	0
T34	1273	0	0	0
T39	1176	3	0	0
T40	1532	2	0	0
T41	1378	0	0	0
T42	0	1	0	0
T62	0	2	0	0
T89	0	4	0	0
T108	5657	0	0	0
T185	0	2	0	0
T201	0	1	0	0
T202	0	1	0	0
T203	0	2	0	0
T204	0	5	0	0
T205	1171	0	0	0
T206	1577	0	0	0
T207	13398	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	172247520	119	0	0
StatusRise_A	172247520	119	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172247520	119	0	0
T12	484478	0	0	0
T13	243083	0	0	0
T38	1522	1	0	0
T39	1176	4	0	0
T40	1532	2	0	0
T41	1378	0	0	0
T42	0	2	0	0
T62	0	1	0	0
T89	0	4	0	0
T108	5657	0	0	0
T185	0	3	0	0
T201	0	1	0	0
T202	0	3	0	0
T203	0	3	0	0
T205	1171	0	0	0
T206	1577	0	0	0
T207	13398	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172247520	119	0	0
T12	484478	0	0	0
T13	243083	0	0	0
T38	1522	1	0	0
T39	1176	4	0	0
T40	1532	2	0	0
T41	1378	0	0	0
T42	0	2	0	0
T62	0	1	0	0
T89	0	4	0	0
T108	5657	0	0	0
T185	0	3	0	0
T201	0	1	0	0
T202	0	3	0	0
T203	0	3	0	0
T205	1171	0	0	0
T206	1577	0	0	0
T207	13398	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	172247520	130	0	0
StatusRise_A	172247520	130	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172247520	130	0	0
T12	484478	0	0	0
T13	243083	0	0	0
T34	1273	0	0	0
T39	1176	2	0	0
T40	1532	2	0	0
T41	1378	2	0	0
T42	0	2	0	0
T62	0	3	0	0
T89	0	1	0	0
T108	5657	0	0	0
T185	0	3	0	0
T201	0	1	0	0
T202	0	2	0	0
T203	0	5	0	0
T205	1171	0	0	0
T206	1577	0	0	0
T207	13398	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172247520	130	0	0
T12	484478	0	0	0
T13	243083	0	0	0
T34	1273	0	0	0
T39	1176	2	0	0
T40	1532	2	0	0
T41	1378	2	0	0
T42	0	2	0	0
T62	0	3	0	0
T89	0	1	0	0
T108	5657	0	0	0
T185	0	3	0	0
T201	0	1	0	0
T202	0	2	0	0
T203	0	5	0	0
T205	1171	0	0	0
T206	1577	0	0	0
T207	13398	0	0	0