Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T9
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	47718	0	0
CgEnOn_A	2147483647	38195	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	47718	0	0
T1	1675988	256	0	0
T2	1585870	55	0	0
T3	177167	0	0	0
T4	7978	22	0	0
T5	9396	3	0	0
T12	1868495	0	0	0
T13	1500771	0	0	0
T16	19542	3	0	0
T17	4845	3	0	0
T18	9736	7	0	0
T19	4932	3	0	0
T20	9955	3	0	0
T21	5414	3	0	0
T26	0	3	0	0
T38	3172	5	0	0
T39	9435	23	0	0
T40	3575	10	0	0
T41	3069	0	0	0
T42	0	10	0	0
T62	0	5	0	0
T73	0	5	0	0
T108	80796	0	0	0
T185	0	15	0	0
T201	0	5	0	0
T202	0	15	0	0
T203	0	15	0	0
T205	11563	0	0	0
T206	13586	0	0	0
T207	57836	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	38195	0	0
T1	1675988	238	0	0
T2	1585870	37	0	0
T3	177167	0	0	0
T4	7978	19	0	0
T5	9396	0	0	0
T9	0	479	0	0
T11	0	596	0	0
T12	1868495	151	0	0
T13	1500771	0	0	0
T16	19542	0	0	0
T17	4845	0	0	0
T18	9736	4	0	0
T19	4932	0	0	0
T20	9955	0	0	0
T21	5414	0	0	0
T22	0	18	0	0
T28	0	40	0	0
T38	3172	8	0	0
T39	9435	35	0	0
T40	3575	10	0	0
T41	3069	0	0	0
T42	0	10	0	0
T62	0	5	0	0
T73	0	4	0	0
T89	0	4	0	0
T108	80796	0	0	0
T121	0	3	0	0
T185	0	15	0	0
T201	0	5	0	0
T202	0	15	0	0
T203	0	15	0	0
T205	11563	0	0	0
T206	13586	0	0	0
T207	57836	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T9
1	0	Unreachable
1	1	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	245951634	126	0	0
CgEnOn_A	245951634	126	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	245951634	126	0	0
T12	103806	0	0	0
T13	333609	0	0	0
T38	678	1	0	0
T39	2076	4	0	0
T40	786	2	0	0
T41	677	0	0	0
T42	0	2	0	0
T62	0	1	0	0
T73	0	1	0	0
T108	14216	0	0	0
T185	0	3	0	0
T201	0	1	0	0
T202	0	3	0	0
T203	0	3	0	0
T205	2749	0	0	0
T206	3011	0	0	0
T207	12844	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	245951634	126	0	0
T12	103806	0	0	0
T13	333609	0	0	0
T38	678	1	0	0
T39	2076	4	0	0
T40	786	2	0	0
T41	677	0	0	0
T42	0	2	0	0
T62	0	1	0	0
T73	0	1	0	0
T108	14216	0	0	0
T185	0	3	0	0
T201	0	1	0	0
T202	0	3	0	0
T203	0	3	0	0
T205	2749	0	0	0
T206	3011	0	0	0
T207	12844	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T9
1	0	Unreachable
1	1	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	122975165	126	0	0
CgEnOn_A	122975165	126	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122975165	126	0	0
T12	519029	0	0	0
T13	166803	0	0	0
T38	339	1	0	0
T39	1038	4	0	0
T40	393	2	0	0
T41	338	0	0	0
T42	0	2	0	0
T62	0	1	0	0
T73	0	1	0	0
T108	7108	0	0	0
T185	0	3	0	0
T201	0	1	0	0
T202	0	3	0	0
T203	0	3	0	0
T205	1375	0	0	0
T206	1505	0	0	0
T207	6422	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122975165	126	0	0
T12	519029	0	0	0
T13	166803	0	0	0
T38	339	1	0	0
T39	1038	4	0	0
T40	393	2	0	0
T41	338	0	0	0
T42	0	2	0	0
T62	0	1	0	0
T73	0	1	0	0
T108	7108	0	0	0
T185	0	3	0	0
T201	0	1	0	0
T202	0	3	0	0
T203	0	3	0	0
T205	1375	0	0	0
T206	1505	0	0	0
T207	6422	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T9
1	0	Unreachable
1	1	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	122975165	126	0	0
CgEnOn_A	122975165	126	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122975165	126	0	0
T12	519029	0	0	0
T13	166803	0	0	0
T38	339	1	0	0
T39	1038	4	0	0
T40	393	2	0	0
T41	338	0	0	0
T42	0	2	0	0
T62	0	1	0	0
T73	0	1	0	0
T108	7108	0	0	0
T185	0	3	0	0
T201	0	1	0	0
T202	0	3	0	0
T203	0	3	0	0
T205	1375	0	0	0
T206	1505	0	0	0
T207	6422	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122975165	126	0	0
T12	519029	0	0	0
T13	166803	0	0	0
T38	339	1	0	0
T39	1038	4	0	0
T40	393	2	0	0
T41	338	0	0	0
T42	0	2	0	0
T62	0	1	0	0
T73	0	1	0	0
T108	7108	0	0	0
T185	0	3	0	0
T201	0	1	0	0
T202	0	3	0	0
T203	0	3	0	0
T205	1375	0	0	0
T206	1505	0	0	0
T207	6422	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T9
1	0	Unreachable
1	1	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	122975165	126	0	0
CgEnOn_A	122975165	126	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122975165	126	0	0
T12	519029	0	0	0
T13	166803	0	0	0
T38	339	1	0	0
T39	1038	4	0	0
T40	393	2	0	0
T41	338	0	0	0
T42	0	2	0	0
T62	0	1	0	0
T73	0	1	0	0
T108	7108	0	0	0
T185	0	3	0	0
T201	0	1	0	0
T202	0	3	0	0
T203	0	3	0	0
T205	1375	0	0	0
T206	1505	0	0	0
T207	6422	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122975165	126	0	0
T12	519029	0	0	0
T13	166803	0	0	0
T38	339	1	0	0
T39	1038	4	0	0
T40	393	2	0	0
T41	338	0	0	0
T42	0	2	0	0
T62	0	1	0	0
T73	0	1	0	0
T108	7108	0	0	0
T185	0	3	0	0
T201	0	1	0	0
T202	0	3	0	0
T203	0	3	0	0
T205	1375	0	0	0
T206	1505	0	0	0
T207	6422	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T9
1	0	Unreachable
1	1	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	492120848	126	0	0
CgEnOn_A	492120848	120	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492120848	126	0	0
T12	207602	0	0	0
T13	666753	0	0	0
T38	1477	1	0	0
T39	4245	4	0	0
T40	1610	2	0	0
T41	1378	0	0	0
T42	0	2	0	0
T62	0	1	0	0
T73	0	1	0	0
T108	45256	0	0	0
T185	0	3	0	0
T201	0	1	0	0
T202	0	3	0	0
T203	0	3	0	0
T205	4689	0	0	0
T206	6060	0	0	0
T207	25726	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492120848	120	0	0
T12	207602	0	0	0
T13	666753	0	0	0
T38	1477	1	0	0
T39	4245	4	0	0
T40	1610	2	0	0
T41	1378	0	0	0
T42	0	2	0	0
T62	0	1	0	0
T89	0	4	0	0
T108	45256	0	0	0
T185	0	3	0	0
T201	0	1	0	0
T202	0	3	0	0
T203	0	3	0	0
T205	4689	0	0	0
T206	6060	0	0	0
T207	25726	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T9
1	0	Unreachable
1	1	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	524066189	130	0	0
CgEnOn_A	524066189	126	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524066189	130	0	0
T12	218839	0	0	0
T13	705754	0	0	0
T34	1273	0	0	0
T39	4318	3	0	0
T40	1712	2	0	0
T41	1436	0	0	0
T42	0	1	0	0
T62	0	2	0	0
T89	0	4	0	0
T108	47143	0	0	0
T185	0	2	0	0
T201	0	1	0	0
T202	0	1	0	0
T203	0	2	0	0
T204	0	5	0	0
T205	4884	0	0	0
T206	6312	0	0	0
T207	26799	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524066189	126	0	0
T12	218839	0	0	0
T13	705754	0	0	0
T34	1273	0	0	0
T39	4318	3	0	0
T40	1712	2	0	0
T41	1436	0	0	0
T42	0	1	0	0
T62	0	2	0	0
T89	0	4	0	0
T108	47143	0	0	0
T185	0	2	0	0
T201	0	1	0	0
T202	0	1	0	0
T203	0	2	0	0
T204	0	5	0	0
T205	4884	0	0	0
T206	6312	0	0	0
T207	26799	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T9
1	0	Unreachable
1	1	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	524066189	130	0	0
CgEnOn_A	524066189	126	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524066189	130	0	0
T12	218839	0	0	0
T13	705754	0	0	0
T34	1273	0	0	0
T39	4318	3	0	0
T40	1712	2	0	0
T41	1436	0	0	0
T42	0	1	0	0
T62	0	2	0	0
T89	0	4	0	0
T108	47143	0	0	0
T185	0	2	0	0
T201	0	1	0	0
T202	0	1	0	0
T203	0	2	0	0
T204	0	5	0	0
T205	4884	0	0	0
T206	6312	0	0	0
T207	26799	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524066189	126	0	0
T12	218839	0	0	0
T13	705754	0	0	0
T34	1273	0	0	0
T39	4318	3	0	0
T40	1712	2	0	0
T41	1436	0	0	0
T42	0	1	0	0
T62	0	2	0	0
T89	0	4	0	0
T108	47143	0	0	0
T185	0	2	0	0
T201	0	1	0	0
T202	0	1	0	0
T203	0	2	0	0
T204	0	5	0	0
T205	4884	0	0	0
T206	6312	0	0	0
T207	26799	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T9
1	0	Unreachable
1	1	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	251464983	130	0	0
CgEnOn_A	251464983	130	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	251464983	130	0	0
T12	105016	0	0	0
T13	341744	0	0	0
T34	612	0	0	0
T39	2170	2	0	0
T40	822	2	0	0
T41	670	2	0	0
T42	0	2	0	0
T62	0	3	0	0
T89	0	1	0	0
T108	22629	0	0	0
T185	0	3	0	0
T201	0	1	0	0
T202	0	2	0	0
T203	0	5	0	0
T205	2344	0	0	0
T206	3029	0	0	0
T207	9983	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	251464983	130	0	0
T12	105016	0	0	0
T13	341744	0	0	0
T34	612	0	0	0
T39	2170	2	0	0
T40	822	2	0	0
T41	670	2	0	0
T42	0	2	0	0
T62	0	3	0	0
T89	0	1	0	0
T108	22629	0	0	0
T185	0	3	0	0
T201	0	1	0	0
T202	0	2	0	0
T203	0	5	0	0
T205	2344	0	0	0
T206	3029	0	0	0
T207	9983	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T38,T39,T40
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	122975165	7473	0	0
CgEnOn_A	122975165	5103	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122975165	7473	0	0
T1	823867	68	0	0
T2	131709	17	0	0
T4	1132	8	0	0
T5	1329	1	0	0
T16	1910	1	0	0
T17	432	1	0	0
T18	847	1	0	0
T19	440	1	0	0
T20	884	1	0	0
T21	498	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122975165	5103	0	0
T1	823867	62	0	0
T2	131709	11	0	0
T4	1132	7	0	0
T5	1329	0	0	0
T9	0	139	0	0
T11	0	152	0	0
T12	0	151	0	0
T16	1910	0	0	0
T17	432	0	0	0
T18	847	0	0	0
T19	440	0	0	0
T20	884	0	0	0
T21	498	0	0	0
T22	0	6	0	0
T28	0	13	0	0
T38	0	1	0	0
T39	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T38,T39,T40
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	245951634	7567	0	0
CgEnOn_A	245951634	5197	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	245951634	7567	0	0
T1	164774	72	0	0
T2	263417	18	0	0
T4	2265	7	0	0
T5	2658	1	0	0
T16	3820	1	0	0
T17	865	1	0	0
T18	1695	1	0	0
T19	881	1	0	0
T20	1768	1	0	0
T21	998	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	245951634	5197	0	0
T1	164774	66	0	0
T2	263417	12	0	0
T4	2265	6	0	0
T5	2658	0	0	0
T9	0	134	0	0
T11	0	149	0	0
T16	3820	0	0	0
T17	865	0	0	0
T18	1695	0	0	0
T19	881	0	0	0
T20	1768	0	0	0
T21	998	0	0	0
T22	0	6	0	0
T28	0	14	0	0
T38	0	1	0	0
T39	0	4	0	0
T121	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T38,T39,T40
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	492120848	7508	0	0
CgEnOn_A	492120848	5132	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492120848	7508	0	0
T1	329895	74	0	0
T2	527376	19	0	0
T4	4581	7	0	0
T5	5409	1	0	0
T16	6765	1	0	0
T17	1738	1	0	0
T18	3523	1	0	0
T19	1768	1	0	0
T20	3577	1	0	0
T21	1919	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492120848	5132	0	0
T1	329895	68	0	0
T2	527376	13	0	0
T4	4581	6	0	0
T5	5409	0	0	0
T9	0	132	0	0
T11	0	151	0	0
T16	6765	0	0	0
T17	1738	0	0	0
T18	3523	0	0	0
T19	1768	0	0	0
T20	3577	0	0	0
T21	1919	0	0	0
T22	0	6	0	0
T28	0	13	0	0
T38	0	1	0	0
T39	0	4	0	0
T121	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T39,T40,T41
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	251464983	7525	0	0
CgEnOn_A	251464983	5148	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	251464983	7525	0	0
T1	170139	74	0	0
T2	304022	17	0	0
T4	2290	6	0	0
T5	2705	1	0	0
T16	3382	1	0	0
T17	868	1	0	0
T18	1761	1	0	0
T19	884	1	0	0
T20	1788	1	0	0
T21	960	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	251464983	5148	0	0
T1	170139	68	0	0
T2	304022	11	0	0
T4	2290	5	0	0
T5	2705	0	0	0
T9	0	133	0	0
T11	0	145	0	0
T12	0	155	0	0
T16	3382	0	0	0
T17	868	0	0	0
T18	1761	0	0	0
T19	884	0	0	0
T20	1788	0	0	0
T21	960	0	0	0
T22	0	7	0	0
T28	0	14	0	0
T39	0	2	0	0
T121	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T9
1	0	Covered	T1,T18,T2
1	1	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	524066189	4111	0	0
CgEnOn_A	524066189	4107	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524066189	4111	0	0
T1	357452	42	0	0
T2	663368	1	0	0
T3	177167	0	0	0
T9	0	74	0	0
T11	0	144	0	0
T16	7047	0	0	0
T17	1810	0	0	0
T18	3671	4	0	0
T19	1843	0	0	0
T20	3726	0	0	0
T21	1999	0	0	0
T22	1625	0	0	0
T26	0	3	0	0
T39	0	3	0	0
T121	0	1	0	0
T122	0	11	0	0
T123	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524066189	4107	0	0
T1	357452	42	0	0
T2	663368	1	0	0
T3	177167	0	0	0
T9	0	74	0	0
T11	0	144	0	0
T16	7047	0	0	0
T17	1810	0	0	0
T18	3671	4	0	0
T19	1843	0	0	0
T20	3726	0	0	0
T21	1999	0	0	0
T22	1625	0	0	0
T26	0	3	0	0
T39	0	3	0	0
T121	0	1	0	0
T122	0	11	0	0
T123	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T9
1	0	Covered	T5,T1,T18
1	1	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	524066189	4099	0	0
CgEnOn_A	524066189	4095	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524066189	4099	0	0
T1	357452	33	0	0
T2	663368	1	0	0
T3	177167	0	0	0
T5	5635	1	0	0
T9	0	65	0	0
T11	0	138	0	0
T16	7047	0	0	0
T17	1810	0	0	0
T18	3671	8	0	0
T19	1843	0	0	0
T20	3726	0	0	0
T21	1999	0	0	0
T26	0	4	0	0
T121	0	1	0	0
T122	0	11	0	0
T123	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524066189	4095	0	0
T1	357452	33	0	0
T2	663368	1	0	0
T3	177167	0	0	0
T5	5635	1	0	0
T9	0	65	0	0
T11	0	138	0	0
T16	7047	0	0	0
T17	1810	0	0	0
T18	3671	8	0	0
T19	1843	0	0	0
T20	3726	0	0	0
T21	1999	0	0	0
T26	0	4	0	0
T121	0	1	0	0
T122	0	11	0	0
T123	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T9
1	0	Covered	T1,T18,T2
1	1	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	524066189	4247	0	0
CgEnOn_A	524066189	4243	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524066189	4247	0	0
T1	357452	35	0	0
T2	663368	1	0	0
T3	177167	0	0	0
T9	0	65	0	0
T11	0	146	0	0
T16	7047	0	0	0
T17	1810	0	0	0
T18	3671	12	0	0
T19	1843	0	0	0
T20	3726	0	0	0
T21	1999	0	0	0
T22	1625	0	0	0
T26	0	9	0	0
T39	0	3	0	0
T121	0	1	0	0
T122	0	11	0	0
T123	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524066189	4243	0	0
T1	357452	35	0	0
T2	663368	1	0	0
T3	177167	0	0	0
T9	0	65	0	0
T11	0	146	0	0
T16	7047	0	0	0
T17	1810	0	0	0
T18	3671	12	0	0
T19	1843	0	0	0
T20	3726	0	0	0
T21	1999	0	0	0
T22	1625	0	0	0
T26	0	9	0	0
T39	0	3	0	0
T121	0	1	0	0
T122	0	11	0	0
T123	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T9
1	0	Covered	T1,T18,T2
1	1	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	524066189	4168	0	0
CgEnOn_A	524066189	4164	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524066189	4168	0	0
T1	357452	41	0	0
T2	663368	1	0	0
T3	177167	0	0	0
T9	0	67	0	0
T11	0	147	0	0
T16	7047	0	0	0
T17	1810	0	0	0
T18	3671	9	0	0
T19	1843	0	0	0
T20	3726	0	0	0
T21	1999	0	0	0
T22	1625	0	0	0
T26	0	7	0	0
T39	0	3	0	0
T121	0	1	0	0
T122	0	9	0	0
T123	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524066189	4164	0	0
T1	357452	41	0	0
T2	663368	1	0	0
T3	177167	0	0	0
T9	0	67	0	0
T11	0	147	0	0
T16	7047	0	0	0
T17	1810	0	0	0
T18	3671	9	0	0
T19	1843	0	0	0
T20	3726	0	0	0
T21	1999	0	0	0
T22	1625	0	0	0
T26	0	7	0	0
T39	0	3	0	0
T121	0	1	0	0
T122	0	9	0	0
T123	0	5	0	0