SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::PutFullData_mask_not_match_size | 100.00 | 1 | 100 | 1 | 64 | 64 |
uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::addr_not_align_mask | 100.00 | 1 | 100 | 1 | 64 | 64 |
uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::addr_not_align_size | 100.00 | 1 | 100 | 1 | 64 | 64 |
uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::invalid_a_opcode | 100.00 | 1 | 100 | 1 | 64 | 64 |
uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::mask_not_in_enabled_lanes | 100.00 | 1 | 100 | 1 | 64 | 64 |
uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::size_over_max | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 4 | 0 | 4 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_transitions | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 0 | |
cp_value | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 4 | 0 | 4 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_transitions | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 0 | |
cp_value | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 4 | 0 | 4 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_transitions | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 0 | |
cp_value | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 4 | 0 | 4 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_transitions | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 0 | |
cp_value | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 4 | 0 | 4 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_transitions | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 0 | |
cp_value | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 4 | 0 | 4 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_transitions | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 0 | |
cp_value | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 941220 | 1 | T1 | 41471 | T3 | 10214 | T24 | 11463 | ||||
rising | 941219 | 1 | T1 | 41471 | T3 | 10214 | T24 | 11463 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 5512056 | 1 | T1 | 244824 | T3 | 62024 | T24 | 69120 | ||||
auto[1] | 1166108 | 1 | T1 | 51116 | T3 | 12538 | T24 | 14081 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 1568453 | 1 | T1 | 69488 | T3 | 17520 | T24 | 19734 | ||||
rising | 1568461 | 1 | T1 | 69488 | T3 | 17520 | T24 | 19735 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 4106286 | 1 | T1 | 181504 | T3 | 45596 | T24 | 50482 | ||||
auto[1] | 2571878 | 1 | T1 | 114436 | T3 | 28966 | T24 | 32719 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 1568453 | 1 | T1 | 69488 | T3 | 17520 | T24 | 19734 | ||||
rising | 1568461 | 1 | T1 | 69488 | T3 | 17520 | T24 | 19735 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 4106286 | 1 | T1 | 181504 | T3 | 45596 | T24 | 50482 | ||||
auto[1] | 2571878 | 1 | T1 | 114436 | T3 | 28966 | T24 | 32719 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 1592434 | 1 | T1 | 70763 | T3 | 17915 | T24 | 20116 | ||||
rising | 1592448 | 1 | T1 | 70762 | T3 | 17915 | T24 | 20115 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 3828664 | 1 | T1 | 168763 | T3 | 42357 | T24 | 46491 | ||||
auto[1] | 2849500 | 1 | T1 | 127177 | T3 | 32205 | T24 | 36710 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 1244847 | 1 | T1 | 55347 | T3 | 13901 | T24 | 15294 | ||||
rising | 1244829 | 1 | T1 | 55347 | T3 | 13902 | T24 | 15294 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 5000742 | 1 | T1 | 221713 | T3 | 55758 | T24 | 62713 | ||||
auto[1] | 1677422 | 1 | T1 | 74227 | T3 | 18804 | T24 | 20488 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 1222953 | 1 | T1 | 54483 | T3 | 13597 | T24 | 15243 | ||||
rising | 1222954 | 1 | T1 | 54483 | T3 | 13597 | T24 | 15244 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 5064364 | 1 | T1 | 224109 | T3 | 56560 | T24 | 62945 | ||||
auto[1] | 1613800 | 1 | T1 | 71831 | T3 | 18002 | T24 | 20256 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |