Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	575563	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3255220

1

T1

135731

T4

15

T5

32

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	944623	1			T1	36655		T4	17		T5	33
values[0x0]	1327855	1			T1	53543		T4	19		T5	15
values[0x1]	1558305	1			T1	63744		T4	16		T5	20

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	320121	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3510662

1

T1

145214

T4

20

T5

37

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14862	1			T1	698		T4	1		T2	4
valid_sources[0x01]	14649	1			T1	516		T2	5		T3	139
valid_sources[0x02]	14970	1			T1	689		T16	1		T2	24
valid_sources[0x03]	15220	1			T1	569		T4	1		T2	3
valid_sources[0x04]	14541	1			T1	543		T2	11		T3	155
valid_sources[0x05]	14550	1			T1	678		T2	7		T20	3
valid_sources[0x06]	15589	1			T1	632		T2	6		T20	1
valid_sources[0x07]	16695	1			T1	643		T2	2		T20	1
valid_sources[0x08]	14344	1			T1	639		T5	1		T3	146
valid_sources[0x09]	15456	1			T1	558		T2	5		T20	6
valid_sources[0x0a]	14809	1			T1	569		T2	2		T3	151
valid_sources[0x0b]	14483	1			T1	541		T2	3		T3	151
valid_sources[0x0c]	14836	1			T1	636		T2	8		T3	186
valid_sources[0x0d]	16205	1			T1	429		T4	1		T2	31
valid_sources[0x0e]	14546	1			T1	494		T5	3		T3	158
valid_sources[0x0f]	14807	1			T1	499		T4	1		T5	1
valid_sources[0x10]	15499	1			T1	615		T3	129		T126	2
valid_sources[0x11]	15212	1			T1	549		T3	162		T28	1
valid_sources[0x12]	15376	1			T1	554		T2	5		T3	161
valid_sources[0x13]	15184	1			T1	506		T3	146		T69	1
valid_sources[0x14]	14539	1			T1	442		T2	1		T3	146
valid_sources[0x15]	14096	1			T1	504		T17	2		T3	180
valid_sources[0x16]	16319	1			T1	549		T2	9		T20	1
valid_sources[0x17]	16164	1			T1	602		T3	164		T68	3
valid_sources[0x18]	15290	1			T1	549		T4	1		T2	4
valid_sources[0x19]	15795	1			T1	515		T3	159		T28	1
valid_sources[0x1a]	15508	1			T1	590		T16	1		T3	167
valid_sources[0x1b]	15507	1			T1	651		T4	1		T2	18
valid_sources[0x1c]	14212	1			T1	589		T2	6		T3	177
valid_sources[0x1d]	14190	1			T1	461		T4	1		T2	4
valid_sources[0x1e]	16735	1			T1	683		T5	1		T2	6
valid_sources[0x1f]	13921	1			T1	519		T2	5		T3	142
valid_sources[0x20]	15036	1			T1	594		T4	1		T3	136
valid_sources[0x21]	14927	1			T1	572		T3	169		T68	1
valid_sources[0x22]	15435	1			T1	525		T4	1		T16	6
valid_sources[0x23]	15429	1			T1	646		T2	2		T3	168
valid_sources[0x24]	13773	1			T1	647		T2	17		T3	154
valid_sources[0x25]	13506	1			T1	570		T2	8		T3	142
valid_sources[0x26]	15614	1			T1	536		T4	2		T2	17
valid_sources[0x27]	14139	1			T1	619		T16	1		T2	31
valid_sources[0x28]	15457	1			T1	654		T5	1		T2	6
valid_sources[0x29]	15202	1			T1	687		T2	1		T3	138
valid_sources[0x2a]	15541	1			T1	517		T2	14		T3	157
valid_sources[0x2b]	15419	1			T1	587		T5	2		T3	147
valid_sources[0x2c]	14270	1			T1	746		T4	2		T3	155
valid_sources[0x2d]	14220	1			T1	544		T4	1		T2	15
valid_sources[0x2e]	15254	1			T1	515		T3	182		T68	1
valid_sources[0x2f]	14572	1			T1	604		T5	6		T16	2
valid_sources[0x30]	14475	1			T1	687		T3	154		T68	1
valid_sources[0x31]	16718	1			T1	538		T4	1		T2	20
valid_sources[0x32]	16256	1			T1	648		T4	1		T2	17
valid_sources[0x33]	13772	1			T1	614		T2	2		T3	159
valid_sources[0x34]	14656	1			T1	599		T5	2		T17	17
valid_sources[0x35]	15871	1			T1	613		T2	25		T3	166
valid_sources[0x36]	14270	1			T1	522		T3	184		T68	1
valid_sources[0x37]	13060	1			T1	545		T3	133		T68	1
valid_sources[0x38]	14311	1			T1	660		T2	2		T20	10
valid_sources[0x39]	14469	1			T1	583		T3	149		T28	1
valid_sources[0x3a]	15035	1			T1	632		T5	3		T20	8
valid_sources[0x3b]	15054	1			T1	736		T2	6		T3	176
valid_sources[0x3c]	14792	1			T1	634		T2	12		T3	157
valid_sources[0x3d]	15274	1			T1	590		T2	10		T3	146
valid_sources[0x3e]	15081	1			T1	583		T2	3		T3	157
valid_sources[0x3f]	13923	1			T1	779		T2	8		T3	154
valid_sources[0x40]	14555	1			T1	783		T2	24		T3	182
valid_sources[0x41]	13803	1			T1	712		T4	1		T2	1
valid_sources[0x42]	14103	1			T1	593		T4	1		T3	182
valid_sources[0x43]	14371	1			T1	631		T3	149		T28	1
valid_sources[0x44]	14859	1			T1	688		T3	167		T28	5
valid_sources[0x45]	14298	1			T1	621		T4	2		T2	2
valid_sources[0x46]	15455	1			T1	538		T3	152		T28	4
valid_sources[0x47]	14479	1			T1	526		T17	4		T3	170
valid_sources[0x48]	14533	1			T1	604		T3	162		T68	1
valid_sources[0x49]	13657	1			T1	615		T5	1		T3	134
valid_sources[0x4a]	15747	1			T1	686		T2	13		T3	132
valid_sources[0x4b]	14633	1			T1	488		T2	2		T3	151
valid_sources[0x4c]	15667	1			T1	567		T5	1		T3	169
valid_sources[0x4d]	14620	1			T1	613		T2	3		T3	153
valid_sources[0x4e]	14573	1			T1	618		T3	173		T69	1
valid_sources[0x4f]	14819	1			T1	585		T2	1		T3	181
valid_sources[0x50]	17616	1			T1	657		T2	11		T20	5
valid_sources[0x51]	14352	1			T1	688		T3	135		T28	2
valid_sources[0x52]	14963	1			T1	551		T2	3		T3	143
valid_sources[0x53]	16587	1			T1	718		T4	1		T3	145
valid_sources[0x54]	15275	1			T1	685		T2	4		T3	157
valid_sources[0x55]	15249	1			T1	595		T2	8		T3	154
valid_sources[0x56]	14694	1			T1	450		T2	2		T3	167
valid_sources[0x57]	15847	1			T1	595		T5	1		T2	1
valid_sources[0x58]	14588	1			T1	578		T5	2		T2	8
valid_sources[0x59]	15681	1			T1	584		T2	1		T3	174
valid_sources[0x5a]	14493	1			T1	579		T2	1		T3	162
valid_sources[0x5b]	14337	1			T1	612		T3	175		T28	8
valid_sources[0x5c]	13481	1			T1	598		T2	16		T20	2
valid_sources[0x5d]	14133	1			T1	567		T5	1		T2	40
valid_sources[0x5e]	15574	1			T1	586		T2	5		T3	150
valid_sources[0x5f]	15408	1			T1	588		T5	1		T3	166
valid_sources[0x60]	14669	1			T1	612		T5	1		T16	2
valid_sources[0x61]	16099	1			T1	508		T2	3		T3	167
valid_sources[0x62]	16030	1			T1	529		T2	23		T20	2
valid_sources[0x63]	14294	1			T1	655		T2	19		T3	129
valid_sources[0x64]	14824	1			T1	504		T2	19		T3	172
valid_sources[0x65]	14476	1			T1	697		T4	1		T2	6
valid_sources[0x66]	15636	1			T1	824		T2	2		T20	3
valid_sources[0x67]	13693	1			T1	597		T2	1		T3	176
valid_sources[0x68]	14870	1			T1	646		T5	2		T2	3
valid_sources[0x69]	16240	1			T1	584		T2	5		T3	162
valid_sources[0x6a]	15954	1			T1	583		T16	2		T3	174
valid_sources[0x6b]	15612	1			T1	530		T4	1		T5	4
valid_sources[0x6c]	16649	1			T1	735		T5	2		T2	33
valid_sources[0x6d]	16097	1			T1	680		T17	1		T3	171
valid_sources[0x6e]	14299	1			T1	538		T3	165		T28	10
valid_sources[0x6f]	15048	1			T1	664		T2	26		T3	147
valid_sources[0x70]	17581	1			T1	722		T2	1		T3	159
valid_sources[0x71]	14903	1			T1	610		T2	6		T3	171
valid_sources[0x72]	15170	1			T1	579		T16	3		T2	25
valid_sources[0x73]	15626	1			T1	613		T4	1		T2	2
valid_sources[0x74]	15113	1			T1	493		T16	2		T2	9
valid_sources[0x75]	14272	1			T1	640		T5	1		T3	155
valid_sources[0x76]	14046	1			T1	613		T5	2		T2	9
valid_sources[0x77]	15293	1			T1	501		T2	1		T3	151
valid_sources[0x78]	14027	1			T1	574		T4	1		T3	172
valid_sources[0x79]	14319	1			T1	510		T16	1		T3	182
valid_sources[0x7a]	16550	1			T1	725		T2	8		T3	164
valid_sources[0x7b]	15391	1			T1	686		T2	7		T3	177
valid_sources[0x7c]	15208	1			T1	688		T2	9		T3	164
valid_sources[0x7d]	14790	1			T1	650		T2	7		T3	143
valid_sources[0x7e]	15000	1			T1	575		T2	2		T3	137
valid_sources[0x7f]	15090	1			T1	537		T5	2		T2	42
valid_sources[0x80]	14009	1			T1	611		T2	25		T3	158

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

823218

1

T1

33705

T4

8

T5

24

values[0x0]

all_enables

biggest_size

1239100

1

T1

51480

T4

5

T5

4

values[0x1]

all_enables

biggest_size

1192902

1

T1

50546

T4

2

T5

4