Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T19,T2
0	1	Covered	T1,T19,T2
1	0	Covered	T1,T4,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T2
1	0	Covered	T37,T38,T39
1	1	Covered	T1,T4,T5

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1191436539	13760	0	0
GateOpen_A	1191436539	20682	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1191436539	13760	0	0
T1	2190220	345	0	0
T2	1353015	15	0	0
T3	0	73	0	0
T4	10145	0	0	0
T5	23973	0	0	0
T9	0	56	0	0
T16	6597	0	0	0
T17	8922	0	0	0
T18	33549	0	0	0
T19	11372	21	0	0
T20	28218	0	0	0
T21	7030	0	0	0
T37	0	4	0	0
T38	0	10	0	0
T68	0	4	0	0
T70	0	20	0	0
T147	0	11	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1191436539	20682	0	0
T1	2190220	365	0	0
T2	1353015	35	0	0
T3	0	85	0	0
T4	10145	4	0	0
T5	23973	0	0	0
T16	6597	4	0	0
T17	8922	4	0	0
T18	33549	0	0	0
T19	11372	21	0	0
T20	28218	0	0	0
T21	7030	4	0	0
T68	0	8	0	0
T70	0	24	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T19,T2
0	1	Covered	T1,T19,T2
1	0	Covered	T1,T4,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T2
1	0	Covered	T37,T38,T39
1	1	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	131609258	3290	0	0
GateOpen_A	131609258	5019	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131609258	3290	0	0
T1	403682	83	0	0
T2	147691	3	0	0
T3	0	16	0	0
T4	1222	0	0	0
T5	2999	0	0	0
T9	0	13	0	0
T16	729	0	0	0
T17	1053	0	0	0
T18	3719	0	0	0
T19	1253	5	0	0
T20	3118	0	0	0
T21	775	0	0	0
T37	0	1	0	0
T38	0	2	0	0
T68	0	1	0	0
T70	0	6	0	0
T147	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131609258	5019	0	0
T1	403682	88	0	0
T2	147691	8	0	0
T3	0	19	0	0
T4	1222	1	0	0
T5	2999	0	0	0
T16	729	1	0	0
T17	1053	1	0	0
T18	3719	0	0	0
T19	1253	5	0	0
T20	3118	0	0	0
T21	775	1	0	0
T68	0	2	0	0
T70	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T19,T2
0	1	Covered	T1,T19,T2
1	0	Covered	T1,T4,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T2
1	0	Covered	T37,T38,T39
1	1	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	263219293	3497	0	0
GateOpen_A	263219293	5226	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	263219293	3497	0	0
T1	807368	85	0	0
T2	295379	4	0	0
T3	0	18	0	0
T4	2444	0	0	0
T5	6000	0	0	0
T9	0	14	0	0
T16	1458	0	0	0
T17	2107	0	0	0
T18	7438	0	0	0
T19	2505	6	0	0
T20	6235	0	0	0
T21	1549	0	0	0
T37	0	1	0	0
T38	0	2	0	0
T68	0	1	0	0
T70	0	5	0	0
T147	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	263219293	5226	0	0
T1	807368	90	0	0
T2	295379	9	0	0
T3	0	21	0	0
T4	2444	1	0	0
T5	6000	0	0	0
T16	1458	1	0	0
T17	2107	1	0	0
T18	7438	0	0	0
T19	2505	6	0	0
T20	6235	0	0	0
T21	1549	1	0	0
T68	0	2	0	0
T70	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T19,T2
0	1	Covered	T1,T19,T2
1	0	Covered	T1,T4,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T2
1	0	Covered	T37,T38,T39
1	1	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	527840298	3487	0	0
GateOpen_A	527840298	5219	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527840298	3487	0	0
T1	161508	87	0	0
T2	591260	4	0	0
T3	0	19	0	0
T4	4319	0	0	0
T5	9982	0	0	0
T9	0	13	0	0
T16	2940	0	0	0
T17	3841	0	0	0
T18	14928	0	0	0
T19	5076	5	0	0
T20	12577	0	0	0
T21	3137	0	0	0
T37	0	1	0	0
T38	0	2	0	0
T68	0	1	0	0
T70	0	5	0	0
T147	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527840298	5219	0	0
T1	161508	92	0	0
T2	591260	9	0	0
T3	0	22	0	0
T4	4319	1	0	0
T5	9982	0	0	0
T16	2940	1	0	0
T17	3841	1	0	0
T18	14928	0	0	0
T19	5076	5	0	0
T20	12577	0	0	0
T21	3137	1	0	0
T68	0	2	0	0
T70	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T19,T2
0	1	Covered	T1,T19,T2
1	0	Covered	T1,T4,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T2
1	0	Covered	T37,T38,T39
1	1	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	268767690	3486	0	0
GateOpen_A	268767690	5218	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	268767690	3486	0	0
T1	817662	90	0	0
T2	318685	4	0	0
T3	0	20	0	0
T4	2160	0	0	0
T5	4992	0	0	0
T9	0	16	0	0
T16	1470	0	0	0
T17	1921	0	0	0
T18	7464	0	0	0
T19	2538	5	0	0
T20	6288	0	0	0
T21	1569	0	0	0
T37	0	1	0	0
T38	0	4	0	0
T68	0	1	0	0
T70	0	4	0	0
T147	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	268767690	5218	0	0
T1	817662	95	0	0
T2	318685	9	0	0
T3	0	23	0	0
T4	2160	1	0	0
T5	4992	0	0	0
T16	1470	1	0	0
T17	1921	1	0	0
T18	7464	0	0	0
T19	2538	5	0	0
T20	6288	0	0	0
T21	1569	1	0	0
T68	0	2	0	0
T70	0	5	0	0