Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	752227185	67407	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	752227185	67407	0	0
T1	2146545	964	0	0
T2	3301885	327	0	0
T3	0	450	0	0
T4	10800	0	0	0
T5	12475	0	0	0
T9	0	317	0	0
T10	0	218	0	0
T11	0	268	0	0
T12	0	52	0	0
T13	0	88	0	0
T14	0	86	0	0
T15	0	223	0	0
T16	9495	0	0	0
T17	9395	0	0	0
T18	10105	0	0	0
T19	4490	0	0	0
T20	16370	0	0	0
T21	16330	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	150445437	9904	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150445437	9904	0	0
T1	429309	155	0	0
T2	660377	49	0	0
T3	0	71	0	0
T4	2160	0	0	0
T5	2495	0	0	0
T9	0	47	0	0
T10	0	28	0	0
T11	0	38	0	0
T12	0	8	0	0
T13	0	14	0	0
T14	0	11	0	0
T15	0	33	0	0
T16	1899	0	0	0
T17	1879	0	0	0
T18	2021	0	0	0
T19	898	0	0	0
T20	3274	0	0	0
T21	3266	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	150445437	9727	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150445437	9727	0	0
T1	429309	151	0	0
T2	660377	42	0	0
T3	0	70	0	0
T4	2160	0	0	0
T5	2495	0	0	0
T9	0	39	0	0
T10	0	31	0	0
T11	0	38	0	0
T12	0	8	0	0
T13	0	14	0	0
T14	0	11	0	0
T15	0	28	0	0
T16	1899	0	0	0
T17	1879	0	0	0
T18	2021	0	0	0
T19	898	0	0	0
T20	3274	0	0	0
T21	3266	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	150445437	13670	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150445437	13670	0	0
T1	429309	194	0	0
T2	660377	64	0	0
T3	0	91	0	0
T4	2160	0	0	0
T5	2495	0	0	0
T9	0	63	0	0
T10	0	43	0	0
T11	0	53	0	0
T12	0	11	0	0
T13	0	18	0	0
T14	0	17	0	0
T15	0	45	0	0
T16	1899	0	0	0
T17	1879	0	0	0
T18	2021	0	0	0
T19	898	0	0	0
T20	3274	0	0	0
T21	3266	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	150445437	13522	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150445437	13522	0	0
T1	429309	196	0	0
T2	660377	65	0	0
T3	0	91	0	0
T4	2160	0	0	0
T5	2495	0	0	0
T9	0	65	0	0
T10	0	42	0	0
T11	0	55	0	0
T12	0	11	0	0
T13	0	18	0	0
T14	0	18	0	0
T15	0	44	0	0
T16	1899	0	0	0
T17	1879	0	0	0
T18	2021	0	0	0
T19	898	0	0	0
T20	3274	0	0	0
T21	3266	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	150445437	20584	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150445437	20584	0	0
T1	429309	268	0	0
T2	660377	107	0	0
T3	0	127	0	0
T4	2160	0	0	0
T5	2495	0	0	0
T9	0	103	0	0
T10	0	74	0	0
T11	0	84	0	0
T12	0	14	0	0
T13	0	24	0	0
T14	0	29	0	0
T15	0	73	0	0
T16	1899	0	0	0
T17	1879	0	0	0
T18	2021	0	0	0
T19	898	0	0	0
T20	3274	0	0	0
T21	3266	0	0	0