SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_clk_main_aes_trans.u_idle_cnt | 100.00 | 100.00 | |||||
tb.dut.u_clk_main_hmac_trans.u_idle_cnt | 100.00 | 100.00 | |||||
tb.dut.u_clk_main_kmac_trans.u_idle_cnt | 100.00 | 100.00 | |||||
tb.dut.u_clk_main_otbn_trans.u_idle_cnt | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | u_clk_main_aes_trans |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | u_clk_main_hmac_trans |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | u_clk_main_kmac_trans |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | u_clk_main_otbn_trans |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Total | Covered | Percent | |
---|---|---|---|
Totals | 7 | 7 | 100.00 |
Total Bits | 26 | 26 | 100.00 |
Total Bits 0->1 | 13 | 13 | 100.00 |
Total Bits 1->0 | 13 | 13 | 100.00 |
Ports | 7 | 7 | 100.00 |
Port Bits | 26 | 26 | 100.00 |
Port Bits 0->1 | 13 | 13 | 100.00 |
Port Bits 1->0 | 13 | 13 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T4,T5 | Yes | T1,T4,T5 | INPUT |
rst_ni | Yes | Yes | T1,T2,T3 | Yes | T1,T4,T5 | INPUT |
clr_i | Yes | Yes | T1,T4,T5 | Yes | T1,T4,T5 | INPUT |
set_i | Unreachable | Unreachable | Unreachable | INPUT | ||
set_cnt_i[3:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
incr_en_i | Yes | Yes | T1,T4,T5 | Yes | T1,T4,T5 | INPUT |
decr_en_i | Unreachable | Unreachable | Unreachable | INPUT | ||
step_i[3:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
commit_i | Unreachable | Unreachable | Unreachable | INPUT | ||
cnt_o[3:0] | Yes | Yes | T1,T4,T5 | Yes | T1,T4,T5 | OUTPUT |
cnt_after_commit_o[3:0] | Yes | Yes | T1,T4,T5 | Yes | T1,T4,T5 | OUTPUT |
err_o | Yes | Yes | T40,T52,T42 | Yes | T40,T52,T42 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 7 | 7 | 100.00 |
Total Bits | 26 | 26 | 100.00 |
Total Bits 0->1 | 13 | 13 | 100.00 |
Total Bits 1->0 | 13 | 13 | 100.00 |
Ports | 7 | 7 | 100.00 |
Port Bits | 26 | 26 | 100.00 |
Port Bits 0->1 | 13 | 13 | 100.00 |
Port Bits 1->0 | 13 | 13 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T4,T5 | Yes | T1,T4,T5 | INPUT |
rst_ni | Yes | Yes | T1,T2,T3 | Yes | T1,T4,T5 | INPUT |
clr_i | Yes | Yes | T1,T4,T5 | Yes | T1,T4,T5 | INPUT |
set_i | Unreachable | Unreachable | Unreachable | INPUT | ||
set_cnt_i[3:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
incr_en_i | Yes | Yes | T1,T4,T5 | Yes | T1,T4,T5 | INPUT |
decr_en_i | Unreachable | Unreachable | Unreachable | INPUT | ||
step_i[3:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
commit_i | Unreachable | Unreachable | Unreachable | INPUT | ||
cnt_o[3:0] | Yes | Yes | T1,T4,T5 | Yes | T1,T4,T5 | OUTPUT |
cnt_after_commit_o[3:0] | Yes | Yes | T1,T4,T5 | Yes | T1,T4,T5 | OUTPUT |
err_o | Yes | Yes | T40,T52,T42 | Yes | T40,T52,T42 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 7 | 7 | 100.00 |
Total Bits | 26 | 26 | 100.00 |
Total Bits 0->1 | 13 | 13 | 100.00 |
Total Bits 1->0 | 13 | 13 | 100.00 |
Ports | 7 | 7 | 100.00 |
Port Bits | 26 | 26 | 100.00 |
Port Bits 0->1 | 13 | 13 | 100.00 |
Port Bits 1->0 | 13 | 13 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T4,T5 | Yes | T1,T4,T5 | INPUT |
rst_ni | Yes | Yes | T1,T2,T3 | Yes | T1,T4,T5 | INPUT |
clr_i | Yes | Yes | T1,T4,T5 | Yes | T1,T4,T5 | INPUT |
set_i | Unreachable | Unreachable | Unreachable | INPUT | ||
set_cnt_i[3:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
incr_en_i | Yes | Yes | T1,T4,T5 | Yes | T1,T4,T5 | INPUT |
decr_en_i | Unreachable | Unreachable | Unreachable | INPUT | ||
step_i[3:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
commit_i | Unreachable | Unreachable | Unreachable | INPUT | ||
cnt_o[3:0] | Yes | Yes | T1,T4,T5 | Yes | T1,T4,T5 | OUTPUT |
cnt_after_commit_o[3:0] | Yes | Yes | T1,T4,T5 | Yes | T1,T4,T5 | OUTPUT |
err_o | Yes | Yes | T40,T52,T42 | Yes | T40,T52,T42 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 7 | 7 | 100.00 |
Total Bits | 26 | 26 | 100.00 |
Total Bits 0->1 | 13 | 13 | 100.00 |
Total Bits 1->0 | 13 | 13 | 100.00 |
Ports | 7 | 7 | 100.00 |
Port Bits | 26 | 26 | 100.00 |
Port Bits 0->1 | 13 | 13 | 100.00 |
Port Bits 1->0 | 13 | 13 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T4,T5 | Yes | T1,T4,T5 | INPUT |
rst_ni | Yes | Yes | T1,T2,T3 | Yes | T1,T4,T5 | INPUT |
clr_i | Yes | Yes | T1,T4,T5 | Yes | T1,T4,T5 | INPUT |
set_i | Unreachable | Unreachable | Unreachable | INPUT | ||
set_cnt_i[3:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
incr_en_i | Yes | Yes | T1,T4,T5 | Yes | T1,T4,T5 | INPUT |
decr_en_i | Unreachable | Unreachable | Unreachable | INPUT | ||
step_i[3:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
commit_i | Unreachable | Unreachable | Unreachable | INPUT | ||
cnt_o[3:0] | Yes | Yes | T1,T4,T5 | Yes | T1,T4,T5 | OUTPUT |
cnt_after_commit_o[3:0] | Yes | Yes | T1,T4,T5 | Yes | T1,T4,T5 | OUTPUT |
err_o | Yes | Yes | T40,T52,T42 | Yes | T40,T52,T42 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 7 | 7 | 100.00 |
Total Bits | 26 | 26 | 100.00 |
Total Bits 0->1 | 13 | 13 | 100.00 |
Total Bits 1->0 | 13 | 13 | 100.00 |
Ports | 7 | 7 | 100.00 |
Port Bits | 26 | 26 | 100.00 |
Port Bits 0->1 | 13 | 13 | 100.00 |
Port Bits 1->0 | 13 | 13 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T4,T5 | Yes | T1,T4,T5 | INPUT |
rst_ni | Yes | Yes | T1,T2,T3 | Yes | T1,T4,T5 | INPUT |
clr_i | Yes | Yes | T1,T4,T5 | Yes | T1,T4,T5 | INPUT |
set_i | Unreachable | Unreachable | Unreachable | INPUT | ||
set_cnt_i[3:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
incr_en_i | Yes | Yes | T1,T4,T5 | Yes | T1,T4,T5 | INPUT |
decr_en_i | Unreachable | Unreachable | Unreachable | INPUT | ||
step_i[3:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
commit_i | Unreachable | Unreachable | Unreachable | INPUT | ||
cnt_o[3:0] | Yes | Yes | T1,T4,T5 | Yes | T1,T4,T5 | OUTPUT |
cnt_after_commit_o[3:0] | Yes | Yes | T1,T4,T5 | Yes | T1,T4,T5 | OUTPUT |
err_o | Yes | Yes | T40,T52,T42 | Yes | T40,T52,T42 | OUTPUT |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |