Module Definition
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Module Instance : tb.dut.u_clk_main_aes_trans.u_idle_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_aes_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_clk_main_hmac_trans.u_idle_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_hmac_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_clk_main_kmac_trans.u_idle_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_kmac_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_clk_main_otbn_trans.u_idle_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_otbn_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_count
TotalCoveredPercent
Totals 7 7 100.00
Total Bits 26 26 100.00
Total Bits 0->1 13 13 100.00
Total Bits 1->0 13 13 100.00

Ports 7 7 100.00
Port Bits 26 26 100.00
Port Bits 0->1 13 13 100.00
Port Bits 1->0 13 13 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T4,T5 Yes T1,T4,T5 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T4,T5 INPUT
clr_i Yes Yes T1,T4,T5 Yes T1,T4,T5 INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[3:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T4,T5 Yes T1,T4,T5 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[3:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[3:0] Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
cnt_after_commit_o[3:0] Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
err_o Yes Yes T40,T52,T42 Yes T40,T52,T42 OUTPUT

Toggle Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_cnt
TotalCoveredPercent
Totals 7 7 100.00
Total Bits 26 26 100.00
Total Bits 0->1 13 13 100.00
Total Bits 1->0 13 13 100.00

Ports 7 7 100.00
Port Bits 26 26 100.00
Port Bits 0->1 13 13 100.00
Port Bits 1->0 13 13 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T4,T5 Yes T1,T4,T5 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T4,T5 INPUT
clr_i Yes Yes T1,T4,T5 Yes T1,T4,T5 INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[3:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T4,T5 Yes T1,T4,T5 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[3:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[3:0] Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
cnt_after_commit_o[3:0] Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
err_o Yes Yes T40,T52,T42 Yes T40,T52,T42 OUTPUT

Toggle Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_cnt
TotalCoveredPercent
Totals 7 7 100.00
Total Bits 26 26 100.00
Total Bits 0->1 13 13 100.00
Total Bits 1->0 13 13 100.00

Ports 7 7 100.00
Port Bits 26 26 100.00
Port Bits 0->1 13 13 100.00
Port Bits 1->0 13 13 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T4,T5 Yes T1,T4,T5 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T4,T5 INPUT
clr_i Yes Yes T1,T4,T5 Yes T1,T4,T5 INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[3:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T4,T5 Yes T1,T4,T5 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[3:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[3:0] Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
cnt_after_commit_o[3:0] Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
err_o Yes Yes T40,T52,T42 Yes T40,T52,T42 OUTPUT

Toggle Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_cnt
TotalCoveredPercent
Totals 7 7 100.00
Total Bits 26 26 100.00
Total Bits 0->1 13 13 100.00
Total Bits 1->0 13 13 100.00

Ports 7 7 100.00
Port Bits 26 26 100.00
Port Bits 0->1 13 13 100.00
Port Bits 1->0 13 13 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T4,T5 Yes T1,T4,T5 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T4,T5 INPUT
clr_i Yes Yes T1,T4,T5 Yes T1,T4,T5 INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[3:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T4,T5 Yes T1,T4,T5 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[3:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[3:0] Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
cnt_after_commit_o[3:0] Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
err_o Yes Yes T40,T52,T42 Yes T40,T52,T42 OUTPUT

Toggle Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_cnt
TotalCoveredPercent
Totals 7 7 100.00
Total Bits 26 26 100.00
Total Bits 0->1 13 13 100.00
Total Bits 1->0 13 13 100.00

Ports 7 7 100.00
Port Bits 26 26 100.00
Port Bits 0->1 13 13 100.00
Port Bits 1->0 13 13 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T4,T5 Yes T1,T4,T5 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T4,T5 INPUT
clr_i Yes Yes T1,T4,T5 Yes T1,T4,T5 INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[3:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T4,T5 Yes T1,T4,T5 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[3:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[3:0] Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
cnt_after_commit_o[3:0] Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
err_o Yes Yes T40,T52,T42 Yes T40,T52,T42 OUTPUT

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