Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	150445437	147445498	0	0
AllClkBypReqTrue_A	150445437	131880	0	0
IoClkBypReqFalse_A	150445437	147367441	0	2415
IoClkBypReqTrue_A	150445437	205195	0	0
LcClkBypAckFalse_A	150445437	147456648	0	0
LcClkBypAckTrue_A	150445437	120730	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150445437	147445498	0	0
T1	429309	428491	0	0
T2	660377	659246	0	0
T4	2160	1819	0	0
T5	2495	2126	0	0
T16	1899	1802	0	0
T17	1879	1731	0	0
T18	2021	2001	0	0
T19	898	871	0	0
T20	3274	3214	0	0
T21	3266	3111	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150445437	131880	0	0
T1	429309	1918	0	0
T2	660377	46	0	0
T3	0	1328	0	0
T4	2160	286	0	0
T5	2495	348	0	0
T9	0	228	0	0
T16	1899	0	0	0
T17	1879	75	0	0
T18	2021	0	0	0
T19	898	0	0	0
T20	3274	0	0	0
T21	3266	0	0	0
T71	0	133	0	0
T72	0	92	0	0
T102	0	38	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150445437	147367441	0	2415
T1	429309	428315	0	3
T2	660377	659232	0	3
T4	2160	1553	0	3
T5	2495	1881	0	3
T16	1899	1800	0	3
T17	1879	1621	0	3
T18	2021	1999	0	3
T19	898	869	0	3
T20	3274	3212	0	3
T21	3266	3109	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150445437	205195	0	0
T1	429309	3658	0	0
T2	660377	48	0	0
T3	0	2635	0	0
T4	2160	550	0	0
T5	2495	591	0	0
T9	0	267	0	0
T16	1899	0	0	0
T17	1879	183	0	0
T18	2021	0	0	0
T19	898	0	0	0
T20	3274	0	0	0
T21	3266	0	0	0
T71	0	194	0	0
T72	0	582	0	0
T102	0	56	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150445437	147456648	0	0
T1	429309	428476	0	0
T2	660377	659285	0	0
T4	2160	1815	0	0
T5	2495	2203	0	0
T16	1899	1802	0	0
T17	1879	1747	0	0
T18	2021	2001	0	0
T19	898	871	0	0
T20	3274	3214	0	0
T21	3266	3111	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150445437	120730	0	0
T1	429309	2069	0	0
T2	660377	7	0	0
T3	0	1259	0	0
T4	2160	290	0	0
T5	2495	271	0	0
T9	0	162	0	0
T16	1899	0	0	0
T17	1879	59	0	0
T18	2021	0	0	0
T19	898	0	0	0
T20	3274	0	0	0
T21	3266	0	0	0
T71	0	125	0	0
T72	0	269	0	0
T102	0	11	0	0