Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	2147483647	15079	0	0
TransStop_A	2147483647	7746	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15079	0	0
T1	683772	271	0	0
T2	2679660	16	0	0
T3	0	66	0	0
T4	18000	0	0	0
T5	41592	0	0	0
T9	0	67	0	0
T16	12252	19	0	0
T17	16000	0	0	0
T18	62200	26	0	0
T19	21148	0	0	0
T20	52408	41	0	0
T21	13068	39	0	0
T68	0	4	0	0
T69	0	33	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7746	0	0
T1	683772	125	0	0
T2	2679660	16	0	0
T3	0	31	0	0
T4	18000	0	0	0
T5	41592	0	0	0
T9	0	37	0	0
T16	12252	9	0	0
T17	16000	0	0	0
T18	62200	16	0	0
T19	21148	0	0	0
T20	52408	15	0	0
T21	13068	20	0	0
T68	0	4	0	0
T69	0	22	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	560436626	3807	0	0
TransStop_A	560436626	1965	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	560436626	3807	0	0
T1	170943	71	0	0
T2	669915	4	0	0
T3	0	14	0	0
T4	4500	0	0	0
T5	10398	0	0	0
T9	0	17	0	0
T16	3063	3	0	0
T17	4000	0	0	0
T18	15550	7	0	0
T19	5287	0	0	0
T20	13102	10	0	0
T21	3267	11	0	0
T68	0	1	0	0
T69	0	9	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	560436626	1965	0	0
T1	170943	34	0	0
T2	669915	4	0	0
T3	0	7	0	0
T4	4500	0	0	0
T5	10398	0	0	0
T9	0	11	0	0
T16	3063	2	0	0
T17	4000	0	0	0
T18	15550	4	0	0
T19	5287	0	0	0
T20	13102	3	0	0
T21	3267	6	0	0
T68	0	1	0	0
T69	0	7	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	560436626	3716	0	0
TransStop_A	560436626	1933	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	560436626	3716	0	0
T1	170943	58	0	0
T2	669915	4	0	0
T3	0	17	0	0
T4	4500	0	0	0
T5	10398	0	0	0
T9	0	17	0	0
T16	3063	6	0	0
T17	4000	0	0	0
T18	15550	4	0	0
T19	5287	0	0	0
T20	13102	12	0	0
T21	3267	11	0	0
T68	0	1	0	0
T69	0	11	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	560436626	1933	0	0
T1	170943	29	0	0
T2	669915	4	0	0
T3	0	8	0	0
T4	4500	0	0	0
T5	10398	0	0	0
T9	0	10	0	0
T16	3063	3	0	0
T17	4000	0	0	0
T18	15550	1	0	0
T19	5287	0	0	0
T20	13102	5	0	0
T21	3267	5	0	0
T68	0	1	0	0
T69	0	7	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	560436626	3784	0	0
TransStop_A	560436626	1935	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	560436626	3784	0	0
T1	170943	69	0	0
T2	669915	4	0	0
T3	0	19	0	0
T4	4500	0	0	0
T5	10398	0	0	0
T9	0	18	0	0
T16	3063	5	0	0
T17	4000	0	0	0
T18	15550	7	0	0
T19	5287	0	0	0
T20	13102	10	0	0
T21	3267	9	0	0
T68	0	1	0	0
T69	0	6	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	560436626	1935	0	0
T1	170943	31	0	0
T2	669915	4	0	0
T3	0	9	0	0
T4	4500	0	0	0
T5	10398	0	0	0
T9	0	6	0	0
T16	3063	2	0	0
T17	4000	0	0	0
T18	15550	5	0	0
T19	5287	0	0	0
T20	13102	5	0	0
T21	3267	4	0	0
T68	0	1	0	0
T69	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	560436626	3772	0	0
TransStop_A	560436626	1913	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	560436626	3772	0	0
T1	170943	73	0	0
T2	669915	4	0	0
T3	0	16	0	0
T4	4500	0	0	0
T5	10398	0	0	0
T9	0	15	0	0
T16	3063	5	0	0
T17	4000	0	0	0
T18	15550	8	0	0
T19	5287	0	0	0
T20	13102	9	0	0
T21	3267	8	0	0
T68	0	1	0	0
T69	0	7	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	560436626	1913	0	0
T1	170943	31	0	0
T2	669915	4	0	0
T3	0	7	0	0
T4	4500	0	0	0
T5	10398	0	0	0
T9	0	10	0	0
T16	3063	2	0	0
T17	4000	0	0	0
T18	15550	6	0	0
T19	5287	0	0	0
T20	13102	2	0	0
T21	3267	5	0	0
T68	0	1	0	0
T69	0	5	0	0