Module Definition
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Module : clkmgr_lost_calib_regwen_sva_if
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if 100.00 100.00



Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
RegwenOff_A 150445437 14766199 0 63


RegwenOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 150445437 14766199 0 63
T1 429309 110020 0 0
T2 660377 36158 0 0
T3 0 33561 0 0
T4 2160 0 0 0
T5 2495 0 0 0
T9 0 35804 0 0
T10 0 25284 0 1
T11 0 26466 0 0
T12 0 4595 0 1
T13 0 6713 0 0
T14 0 12719 0 1
T15 0 24127 0 1
T16 1899 0 0 0
T17 1879 0 0 0
T18 2021 0 0 0
T19 898 0 0 0
T20 3274 0 0 0
T21 3266 0 0 0
T23 0 0 0 1
T26 0 0 0 1
T103 0 0 0 1
T104 0 0 0 1
T105 0 0 0 1
T106 0 0 0 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%