Line Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Module :
prim_pulse_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Module :
prim_pulse_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
913458 |
0 |
0 |
T1 |
3587546 |
9128 |
0 |
0 |
T2 |
2955378 |
2054 |
0 |
0 |
T3 |
0 |
1080 |
0 |
0 |
T4 |
19530 |
0 |
0 |
0 |
T5 |
43870 |
0 |
0 |
0 |
T9 |
0 |
1220 |
0 |
0 |
T10 |
0 |
176 |
0 |
0 |
T11 |
0 |
2536 |
0 |
0 |
T12 |
0 |
140 |
0 |
0 |
T16 |
13000 |
0 |
0 |
0 |
T17 |
17093 |
0 |
0 |
0 |
T18 |
58527 |
0 |
0 |
0 |
T19 |
20023 |
0 |
0 |
0 |
T20 |
50774 |
0 |
0 |
0 |
T21 |
15089 |
0 |
0 |
0 |
T28 |
0 |
120 |
0 |
0 |
T29 |
0 |
100 |
0 |
0 |
T30 |
0 |
760 |
0 |
0 |
T31 |
0 |
1050 |
0 |
0 |
T54 |
17712 |
2 |
0 |
0 |
T55 |
15872 |
1 |
0 |
0 |
T56 |
9169 |
0 |
0 |
0 |
T57 |
4504 |
2 |
0 |
0 |
T58 |
6908 |
2 |
0 |
0 |
T73 |
0 |
88 |
0 |
0 |
T107 |
20278 |
2 |
0 |
0 |
T108 |
26980 |
1 |
0 |
0 |
T109 |
17838 |
1 |
0 |
0 |
T110 |
21124 |
3 |
0 |
0 |
T111 |
9052 |
3 |
0 |
0 |
T112 |
5889 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
911544 |
0 |
0 |
T1 |
4552842 |
9128 |
0 |
0 |
T2 |
1623377 |
2054 |
0 |
0 |
T3 |
0 |
1080 |
0 |
0 |
T4 |
8020 |
0 |
0 |
0 |
T5 |
13897 |
0 |
0 |
0 |
T9 |
0 |
1220 |
0 |
0 |
T10 |
0 |
176 |
0 |
0 |
T11 |
0 |
2536 |
0 |
0 |
T12 |
0 |
140 |
0 |
0 |
T16 |
6111 |
0 |
0 |
0 |
T17 |
6985 |
0 |
0 |
0 |
T18 |
15831 |
0 |
0 |
0 |
T19 |
5780 |
0 |
0 |
0 |
T20 |
16447 |
0 |
0 |
0 |
T21 |
8993 |
0 |
0 |
0 |
T28 |
0 |
120 |
0 |
0 |
T29 |
0 |
100 |
0 |
0 |
T30 |
0 |
760 |
0 |
0 |
T31 |
0 |
1050 |
0 |
0 |
T54 |
15894 |
2 |
0 |
0 |
T55 |
31514 |
1 |
0 |
0 |
T56 |
3932 |
0 |
0 |
0 |
T57 |
20786 |
2 |
0 |
0 |
T58 |
31960 |
2 |
0 |
0 |
T73 |
0 |
88 |
0 |
0 |
T107 |
39078 |
2 |
0 |
0 |
T108 |
25278 |
1 |
0 |
0 |
T109 |
7356 |
1 |
0 |
0 |
T110 |
8552 |
3 |
0 |
0 |
T111 |
3544 |
3 |
0 |
0 |
T112 |
10280 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
530440499 |
23595 |
0 |
0 |
T1 |
161508 |
481 |
0 |
0 |
T2 |
591259 |
114 |
0 |
0 |
T3 |
0 |
80 |
0 |
0 |
T4 |
4318 |
0 |
0 |
0 |
T5 |
9981 |
0 |
0 |
0 |
T9 |
0 |
68 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
124 |
0 |
0 |
T16 |
2939 |
0 |
0 |
0 |
T17 |
3840 |
0 |
0 |
0 |
T18 |
14927 |
0 |
0 |
0 |
T19 |
5075 |
0 |
0 |
0 |
T20 |
12577 |
0 |
0 |
0 |
T21 |
3136 |
0 |
0 |
0 |
T28 |
0 |
24 |
0 |
0 |
T29 |
0 |
20 |
0 |
0 |
T30 |
0 |
28 |
0 |
0 |
T31 |
0 |
38 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151378284 |
23595 |
0 |
0 |
T1 |
429309 |
481 |
0 |
0 |
T2 |
660377 |
114 |
0 |
0 |
T3 |
0 |
80 |
0 |
0 |
T4 |
2160 |
0 |
0 |
0 |
T5 |
2495 |
0 |
0 |
0 |
T9 |
0 |
68 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
124 |
0 |
0 |
T16 |
1899 |
0 |
0 |
0 |
T17 |
1879 |
0 |
0 |
0 |
T18 |
2021 |
0 |
0 |
0 |
T19 |
898 |
0 |
0 |
0 |
T20 |
3274 |
0 |
0 |
0 |
T21 |
3266 |
0 |
0 |
0 |
T28 |
0 |
24 |
0 |
0 |
T29 |
0 |
20 |
0 |
0 |
T30 |
0 |
28 |
0 |
0 |
T31 |
0 |
38 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
530440499 |
29574 |
0 |
0 |
T1 |
161508 |
491 |
0 |
0 |
T2 |
591259 |
114 |
0 |
0 |
T3 |
0 |
85 |
0 |
0 |
T4 |
4318 |
0 |
0 |
0 |
T5 |
9981 |
0 |
0 |
0 |
T9 |
0 |
68 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
124 |
0 |
0 |
T16 |
2939 |
0 |
0 |
0 |
T17 |
3840 |
0 |
0 |
0 |
T18 |
14927 |
0 |
0 |
0 |
T19 |
5075 |
0 |
0 |
0 |
T20 |
12577 |
0 |
0 |
0 |
T21 |
3136 |
0 |
0 |
0 |
T28 |
0 |
48 |
0 |
0 |
T29 |
0 |
40 |
0 |
0 |
T30 |
0 |
28 |
0 |
0 |
T31 |
0 |
38 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151378284 |
29588 |
0 |
0 |
T1 |
429309 |
491 |
0 |
0 |
T2 |
660377 |
114 |
0 |
0 |
T3 |
0 |
85 |
0 |
0 |
T4 |
2160 |
0 |
0 |
0 |
T5 |
2495 |
0 |
0 |
0 |
T9 |
0 |
68 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
124 |
0 |
0 |
T16 |
1899 |
0 |
0 |
0 |
T17 |
1879 |
0 |
0 |
0 |
T18 |
2021 |
0 |
0 |
0 |
T19 |
898 |
0 |
0 |
0 |
T20 |
3274 |
0 |
0 |
0 |
T21 |
3266 |
0 |
0 |
0 |
T28 |
0 |
48 |
0 |
0 |
T29 |
0 |
40 |
0 |
0 |
T30 |
0 |
28 |
0 |
0 |
T31 |
0 |
38 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151378284 |
29558 |
0 |
0 |
T1 |
429309 |
491 |
0 |
0 |
T2 |
660377 |
114 |
0 |
0 |
T3 |
0 |
85 |
0 |
0 |
T4 |
2160 |
0 |
0 |
0 |
T5 |
2495 |
0 |
0 |
0 |
T9 |
0 |
68 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
124 |
0 |
0 |
T16 |
1899 |
0 |
0 |
0 |
T17 |
1879 |
0 |
0 |
0 |
T18 |
2021 |
0 |
0 |
0 |
T19 |
898 |
0 |
0 |
0 |
T20 |
3274 |
0 |
0 |
0 |
T21 |
3266 |
0 |
0 |
0 |
T28 |
0 |
48 |
0 |
0 |
T29 |
0 |
40 |
0 |
0 |
T30 |
0 |
28 |
0 |
0 |
T31 |
0 |
38 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
530440499 |
29581 |
0 |
0 |
T1 |
161508 |
491 |
0 |
0 |
T2 |
591259 |
114 |
0 |
0 |
T3 |
0 |
85 |
0 |
0 |
T4 |
4318 |
0 |
0 |
0 |
T5 |
9981 |
0 |
0 |
0 |
T9 |
0 |
68 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
124 |
0 |
0 |
T16 |
2939 |
0 |
0 |
0 |
T17 |
3840 |
0 |
0 |
0 |
T18 |
14927 |
0 |
0 |
0 |
T19 |
5075 |
0 |
0 |
0 |
T20 |
12577 |
0 |
0 |
0 |
T21 |
3136 |
0 |
0 |
0 |
T28 |
0 |
48 |
0 |
0 |
T29 |
0 |
40 |
0 |
0 |
T30 |
0 |
28 |
0 |
0 |
T31 |
0 |
38 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
264471396 |
23595 |
0 |
0 |
T1 |
807368 |
481 |
0 |
0 |
T2 |
295379 |
114 |
0 |
0 |
T3 |
0 |
80 |
0 |
0 |
T4 |
2444 |
0 |
0 |
0 |
T5 |
5999 |
0 |
0 |
0 |
T9 |
0 |
68 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
124 |
0 |
0 |
T16 |
1457 |
0 |
0 |
0 |
T17 |
2107 |
0 |
0 |
0 |
T18 |
7437 |
0 |
0 |
0 |
T19 |
2504 |
0 |
0 |
0 |
T20 |
6235 |
0 |
0 |
0 |
T21 |
1549 |
0 |
0 |
0 |
T28 |
0 |
24 |
0 |
0 |
T29 |
0 |
20 |
0 |
0 |
T30 |
0 |
28 |
0 |
0 |
T31 |
0 |
38 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151378284 |
23595 |
0 |
0 |
T1 |
429309 |
481 |
0 |
0 |
T2 |
660377 |
114 |
0 |
0 |
T3 |
0 |
80 |
0 |
0 |
T4 |
2160 |
0 |
0 |
0 |
T5 |
2495 |
0 |
0 |
0 |
T9 |
0 |
68 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
124 |
0 |
0 |
T16 |
1899 |
0 |
0 |
0 |
T17 |
1879 |
0 |
0 |
0 |
T18 |
2021 |
0 |
0 |
0 |
T19 |
898 |
0 |
0 |
0 |
T20 |
3274 |
0 |
0 |
0 |
T21 |
3266 |
0 |
0 |
0 |
T28 |
0 |
24 |
0 |
0 |
T29 |
0 |
20 |
0 |
0 |
T30 |
0 |
28 |
0 |
0 |
T31 |
0 |
38 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
264471396 |
29465 |
0 |
0 |
T1 |
807368 |
491 |
0 |
0 |
T2 |
295379 |
114 |
0 |
0 |
T3 |
0 |
85 |
0 |
0 |
T4 |
2444 |
0 |
0 |
0 |
T5 |
5999 |
0 |
0 |
0 |
T9 |
0 |
68 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
124 |
0 |
0 |
T16 |
1457 |
0 |
0 |
0 |
T17 |
2107 |
0 |
0 |
0 |
T18 |
7437 |
0 |
0 |
0 |
T19 |
2504 |
0 |
0 |
0 |
T20 |
6235 |
0 |
0 |
0 |
T21 |
1549 |
0 |
0 |
0 |
T28 |
0 |
48 |
0 |
0 |
T29 |
0 |
40 |
0 |
0 |
T30 |
0 |
28 |
0 |
0 |
T31 |
0 |
38 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151378284 |
29488 |
0 |
0 |
T1 |
429309 |
491 |
0 |
0 |
T2 |
660377 |
114 |
0 |
0 |
T3 |
0 |
85 |
0 |
0 |
T4 |
2160 |
0 |
0 |
0 |
T5 |
2495 |
0 |
0 |
0 |
T9 |
0 |
68 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
124 |
0 |
0 |
T16 |
1899 |
0 |
0 |
0 |
T17 |
1879 |
0 |
0 |
0 |
T18 |
2021 |
0 |
0 |
0 |
T19 |
898 |
0 |
0 |
0 |
T20 |
3274 |
0 |
0 |
0 |
T21 |
3266 |
0 |
0 |
0 |
T28 |
0 |
48 |
0 |
0 |
T29 |
0 |
40 |
0 |
0 |
T30 |
0 |
28 |
0 |
0 |
T31 |
0 |
38 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151378284 |
29455 |
0 |
0 |
T1 |
429309 |
491 |
0 |
0 |
T2 |
660377 |
114 |
0 |
0 |
T3 |
0 |
85 |
0 |
0 |
T4 |
2160 |
0 |
0 |
0 |
T5 |
2495 |
0 |
0 |
0 |
T9 |
0 |
68 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
124 |
0 |
0 |
T16 |
1899 |
0 |
0 |
0 |
T17 |
1879 |
0 |
0 |
0 |
T18 |
2021 |
0 |
0 |
0 |
T19 |
898 |
0 |
0 |
0 |
T20 |
3274 |
0 |
0 |
0 |
T21 |
3266 |
0 |
0 |
0 |
T28 |
0 |
48 |
0 |
0 |
T29 |
0 |
40 |
0 |
0 |
T30 |
0 |
28 |
0 |
0 |
T31 |
0 |
38 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
264471396 |
29470 |
0 |
0 |
T1 |
807368 |
491 |
0 |
0 |
T2 |
295379 |
114 |
0 |
0 |
T3 |
0 |
85 |
0 |
0 |
T4 |
2444 |
0 |
0 |
0 |
T5 |
5999 |
0 |
0 |
0 |
T9 |
0 |
68 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
124 |
0 |
0 |
T16 |
1457 |
0 |
0 |
0 |
T17 |
2107 |
0 |
0 |
0 |
T18 |
7437 |
0 |
0 |
0 |
T19 |
2504 |
0 |
0 |
0 |
T20 |
6235 |
0 |
0 |
0 |
T21 |
1549 |
0 |
0 |
0 |
T28 |
0 |
48 |
0 |
0 |
T29 |
0 |
40 |
0 |
0 |
T30 |
0 |
28 |
0 |
0 |
T31 |
0 |
38 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
132235143 |
23595 |
0 |
0 |
T1 |
403682 |
481 |
0 |
0 |
T2 |
147690 |
114 |
0 |
0 |
T3 |
0 |
80 |
0 |
0 |
T4 |
1221 |
0 |
0 |
0 |
T5 |
2999 |
0 |
0 |
0 |
T9 |
0 |
68 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
124 |
0 |
0 |
T16 |
729 |
0 |
0 |
0 |
T17 |
1053 |
0 |
0 |
0 |
T18 |
3719 |
0 |
0 |
0 |
T19 |
1252 |
0 |
0 |
0 |
T20 |
3117 |
0 |
0 |
0 |
T21 |
774 |
0 |
0 |
0 |
T28 |
0 |
24 |
0 |
0 |
T29 |
0 |
20 |
0 |
0 |
T30 |
0 |
28 |
0 |
0 |
T31 |
0 |
38 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151378284 |
23595 |
0 |
0 |
T1 |
429309 |
481 |
0 |
0 |
T2 |
660377 |
114 |
0 |
0 |
T3 |
0 |
80 |
0 |
0 |
T4 |
2160 |
0 |
0 |
0 |
T5 |
2495 |
0 |
0 |
0 |
T9 |
0 |
68 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
124 |
0 |
0 |
T16 |
1899 |
0 |
0 |
0 |
T17 |
1879 |
0 |
0 |
0 |
T18 |
2021 |
0 |
0 |
0 |
T19 |
898 |
0 |
0 |
0 |
T20 |
3274 |
0 |
0 |
0 |
T21 |
3266 |
0 |
0 |
0 |
T28 |
0 |
24 |
0 |
0 |
T29 |
0 |
20 |
0 |
0 |
T30 |
0 |
28 |
0 |
0 |
T31 |
0 |
38 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
132235143 |
29526 |
0 |
0 |
T1 |
403682 |
491 |
0 |
0 |
T2 |
147690 |
114 |
0 |
0 |
T3 |
0 |
85 |
0 |
0 |
T4 |
1221 |
0 |
0 |
0 |
T5 |
2999 |
0 |
0 |
0 |
T9 |
0 |
68 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
124 |
0 |
0 |
T16 |
729 |
0 |
0 |
0 |
T17 |
1053 |
0 |
0 |
0 |
T18 |
3719 |
0 |
0 |
0 |
T19 |
1252 |
0 |
0 |
0 |
T20 |
3117 |
0 |
0 |
0 |
T21 |
774 |
0 |
0 |
0 |
T28 |
0 |
48 |
0 |
0 |
T29 |
0 |
40 |
0 |
0 |
T30 |
0 |
28 |
0 |
0 |
T31 |
0 |
38 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151378284 |
29556 |
0 |
0 |
T1 |
429309 |
491 |
0 |
0 |
T2 |
660377 |
114 |
0 |
0 |
T3 |
0 |
85 |
0 |
0 |
T4 |
2160 |
0 |
0 |
0 |
T5 |
2495 |
0 |
0 |
0 |
T9 |
0 |
68 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
124 |
0 |
0 |
T16 |
1899 |
0 |
0 |
0 |
T17 |
1879 |
0 |
0 |
0 |
T18 |
2021 |
0 |
0 |
0 |
T19 |
898 |
0 |
0 |
0 |
T20 |
3274 |
0 |
0 |
0 |
T21 |
3266 |
0 |
0 |
0 |
T28 |
0 |
48 |
0 |
0 |
T29 |
0 |
40 |
0 |
0 |
T30 |
0 |
28 |
0 |
0 |
T31 |
0 |
38 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151378284 |
29522 |
0 |
0 |
T1 |
429309 |
491 |
0 |
0 |
T2 |
660377 |
114 |
0 |
0 |
T3 |
0 |
85 |
0 |
0 |
T4 |
2160 |
0 |
0 |
0 |
T5 |
2495 |
0 |
0 |
0 |
T9 |
0 |
68 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
124 |
0 |
0 |
T16 |
1899 |
0 |
0 |
0 |
T17 |
1879 |
0 |
0 |
0 |
T18 |
2021 |
0 |
0 |
0 |
T19 |
898 |
0 |
0 |
0 |
T20 |
3274 |
0 |
0 |
0 |
T21 |
3266 |
0 |
0 |
0 |
T28 |
0 |
48 |
0 |
0 |
T29 |
0 |
40 |
0 |
0 |
T30 |
0 |
28 |
0 |
0 |
T31 |
0 |
38 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
132235143 |
29528 |
0 |
0 |
T1 |
403682 |
491 |
0 |
0 |
T2 |
147690 |
114 |
0 |
0 |
T3 |
0 |
85 |
0 |
0 |
T4 |
1221 |
0 |
0 |
0 |
T5 |
2999 |
0 |
0 |
0 |
T9 |
0 |
68 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
124 |
0 |
0 |
T16 |
729 |
0 |
0 |
0 |
T17 |
1053 |
0 |
0 |
0 |
T18 |
3719 |
0 |
0 |
0 |
T19 |
1252 |
0 |
0 |
0 |
T20 |
3117 |
0 |
0 |
0 |
T21 |
774 |
0 |
0 |
0 |
T28 |
0 |
48 |
0 |
0 |
T29 |
0 |
40 |
0 |
0 |
T30 |
0 |
28 |
0 |
0 |
T31 |
0 |
38 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
563145299 |
23595 |
0 |
0 |
T1 |
170943 |
481 |
0 |
0 |
T2 |
669915 |
114 |
0 |
0 |
T3 |
0 |
80 |
0 |
0 |
T4 |
4499 |
0 |
0 |
0 |
T5 |
10398 |
0 |
0 |
0 |
T9 |
0 |
68 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
124 |
0 |
0 |
T16 |
3062 |
0 |
0 |
0 |
T17 |
4000 |
0 |
0 |
0 |
T18 |
15549 |
0 |
0 |
0 |
T19 |
5286 |
0 |
0 |
0 |
T20 |
13101 |
0 |
0 |
0 |
T21 |
3266 |
0 |
0 |
0 |
T28 |
0 |
24 |
0 |
0 |
T29 |
0 |
20 |
0 |
0 |
T30 |
0 |
28 |
0 |
0 |
T31 |
0 |
38 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151378284 |
23595 |
0 |
0 |
T1 |
429309 |
481 |
0 |
0 |
T2 |
660377 |
114 |
0 |
0 |
T3 |
0 |
80 |
0 |
0 |
T4 |
2160 |
0 |
0 |
0 |
T5 |
2495 |
0 |
0 |
0 |
T9 |
0 |
68 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
124 |
0 |
0 |
T16 |
1899 |
0 |
0 |
0 |
T17 |
1879 |
0 |
0 |
0 |
T18 |
2021 |
0 |
0 |
0 |
T19 |
898 |
0 |
0 |
0 |
T20 |
3274 |
0 |
0 |
0 |
T21 |
3266 |
0 |
0 |
0 |
T28 |
0 |
24 |
0 |
0 |
T29 |
0 |
20 |
0 |
0 |
T30 |
0 |
28 |
0 |
0 |
T31 |
0 |
38 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
563145299 |
29449 |
0 |
0 |
T1 |
170943 |
491 |
0 |
0 |
T2 |
669915 |
114 |
0 |
0 |
T3 |
0 |
85 |
0 |
0 |
T4 |
4499 |
0 |
0 |
0 |
T5 |
10398 |
0 |
0 |
0 |
T9 |
0 |
68 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
124 |
0 |
0 |
T16 |
3062 |
0 |
0 |
0 |
T17 |
4000 |
0 |
0 |
0 |
T18 |
15549 |
0 |
0 |
0 |
T19 |
5286 |
0 |
0 |
0 |
T20 |
13101 |
0 |
0 |
0 |
T21 |
3266 |
0 |
0 |
0 |
T28 |
0 |
48 |
0 |
0 |
T29 |
0 |
40 |
0 |
0 |
T30 |
0 |
28 |
0 |
0 |
T31 |
0 |
38 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151378284 |
29465 |
0 |
0 |
T1 |
429309 |
491 |
0 |
0 |
T2 |
660377 |
114 |
0 |
0 |
T3 |
0 |
85 |
0 |
0 |
T4 |
2160 |
0 |
0 |
0 |
T5 |
2495 |
0 |
0 |
0 |
T9 |
0 |
68 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
124 |
0 |
0 |
T16 |
1899 |
0 |
0 |
0 |
T17 |
1879 |
0 |
0 |
0 |
T18 |
2021 |
0 |
0 |
0 |
T19 |
898 |
0 |
0 |
0 |
T20 |
3274 |
0 |
0 |
0 |
T21 |
3266 |
0 |
0 |
0 |
T28 |
0 |
48 |
0 |
0 |
T29 |
0 |
40 |
0 |
0 |
T30 |
0 |
28 |
0 |
0 |
T31 |
0 |
38 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151378284 |
29439 |
0 |
0 |
T1 |
429309 |
491 |
0 |
0 |
T2 |
660377 |
114 |
0 |
0 |
T3 |
0 |
85 |
0 |
0 |
T4 |
2160 |
0 |
0 |
0 |
T5 |
2495 |
0 |
0 |
0 |
T9 |
0 |
68 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
124 |
0 |
0 |
T16 |
1899 |
0 |
0 |
0 |
T17 |
1879 |
0 |
0 |
0 |
T18 |
2021 |
0 |
0 |
0 |
T19 |
898 |
0 |
0 |
0 |
T20 |
3274 |
0 |
0 |
0 |
T21 |
3266 |
0 |
0 |
0 |
T28 |
0 |
48 |
0 |
0 |
T29 |
0 |
40 |
0 |
0 |
T30 |
0 |
28 |
0 |
0 |
T31 |
0 |
38 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
563145299 |
29452 |
0 |
0 |
T1 |
170943 |
491 |
0 |
0 |
T2 |
669915 |
114 |
0 |
0 |
T3 |
0 |
85 |
0 |
0 |
T4 |
4499 |
0 |
0 |
0 |
T5 |
10398 |
0 |
0 |
0 |
T9 |
0 |
68 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
124 |
0 |
0 |
T16 |
3062 |
0 |
0 |
0 |
T17 |
4000 |
0 |
0 |
0 |
T18 |
15549 |
0 |
0 |
0 |
T19 |
5286 |
0 |
0 |
0 |
T20 |
13101 |
0 |
0 |
0 |
T21 |
3266 |
0 |
0 |
0 |
T28 |
0 |
48 |
0 |
0 |
T29 |
0 |
40 |
0 |
0 |
T30 |
0 |
28 |
0 |
0 |
T31 |
0 |
38 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
270067595 |
23107 |
0 |
0 |
T1 |
817662 |
481 |
0 |
0 |
T2 |
318685 |
114 |
0 |
0 |
T3 |
0 |
80 |
0 |
0 |
T4 |
2160 |
0 |
0 |
0 |
T5 |
4991 |
0 |
0 |
0 |
T9 |
0 |
68 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
124 |
0 |
0 |
T16 |
1469 |
0 |
0 |
0 |
T17 |
1920 |
0 |
0 |
0 |
T18 |
7464 |
0 |
0 |
0 |
T19 |
2537 |
0 |
0 |
0 |
T20 |
6288 |
0 |
0 |
0 |
T21 |
1568 |
0 |
0 |
0 |
T28 |
0 |
12 |
0 |
0 |
T29 |
0 |
10 |
0 |
0 |
T30 |
0 |
28 |
0 |
0 |
T31 |
0 |
38 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151378284 |
23595 |
0 |
0 |
T1 |
429309 |
481 |
0 |
0 |
T2 |
660377 |
114 |
0 |
0 |
T3 |
0 |
80 |
0 |
0 |
T4 |
2160 |
0 |
0 |
0 |
T5 |
2495 |
0 |
0 |
0 |
T9 |
0 |
68 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
124 |
0 |
0 |
T16 |
1899 |
0 |
0 |
0 |
T17 |
1879 |
0 |
0 |
0 |
T18 |
2021 |
0 |
0 |
0 |
T19 |
898 |
0 |
0 |
0 |
T20 |
3274 |
0 |
0 |
0 |
T21 |
3266 |
0 |
0 |
0 |
T28 |
0 |
24 |
0 |
0 |
T29 |
0 |
20 |
0 |
0 |
T30 |
0 |
28 |
0 |
0 |
T31 |
0 |
38 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
270067595 |
29341 |
0 |
0 |
T1 |
817662 |
491 |
0 |
0 |
T2 |
318685 |
114 |
0 |
0 |
T3 |
0 |
85 |
0 |
0 |
T4 |
2160 |
0 |
0 |
0 |
T5 |
4991 |
0 |
0 |
0 |
T9 |
0 |
68 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
124 |
0 |
0 |
T16 |
1469 |
0 |
0 |
0 |
T17 |
1920 |
0 |
0 |
0 |
T18 |
7464 |
0 |
0 |
0 |
T19 |
2537 |
0 |
0 |
0 |
T20 |
6288 |
0 |
0 |
0 |
T21 |
1568 |
0 |
0 |
0 |
T28 |
0 |
36 |
0 |
0 |
T29 |
0 |
33 |
0 |
0 |
T30 |
0 |
28 |
0 |
0 |
T31 |
0 |
38 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151378284 |
29594 |
0 |
0 |
T1 |
429309 |
491 |
0 |
0 |
T2 |
660377 |
114 |
0 |
0 |
T3 |
0 |
85 |
0 |
0 |
T4 |
2160 |
0 |
0 |
0 |
T5 |
2495 |
0 |
0 |
0 |
T9 |
0 |
68 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
124 |
0 |
0 |
T16 |
1899 |
0 |
0 |
0 |
T17 |
1879 |
0 |
0 |
0 |
T18 |
2021 |
0 |
0 |
0 |
T19 |
898 |
0 |
0 |
0 |
T20 |
3274 |
0 |
0 |
0 |
T21 |
3266 |
0 |
0 |
0 |
T28 |
0 |
48 |
0 |
0 |
T29 |
0 |
40 |
0 |
0 |
T30 |
0 |
28 |
0 |
0 |
T31 |
0 |
38 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151378284 |
29249 |
0 |
0 |
T1 |
429309 |
491 |
0 |
0 |
T2 |
660377 |
114 |
0 |
0 |
T3 |
0 |
85 |
0 |
0 |
T4 |
2160 |
0 |
0 |
0 |
T5 |
2495 |
0 |
0 |
0 |
T9 |
0 |
68 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
124 |
0 |
0 |
T16 |
1899 |
0 |
0 |
0 |
T17 |
1879 |
0 |
0 |
0 |
T18 |
2021 |
0 |
0 |
0 |
T19 |
898 |
0 |
0 |
0 |
T20 |
3274 |
0 |
0 |
0 |
T21 |
3266 |
0 |
0 |
0 |
T28 |
0 |
36 |
0 |
0 |
T29 |
0 |
31 |
0 |
0 |
T30 |
0 |
28 |
0 |
0 |
T31 |
0 |
38 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
270067595 |
29380 |
0 |
0 |
T1 |
817662 |
491 |
0 |
0 |
T2 |
318685 |
114 |
0 |
0 |
T3 |
0 |
85 |
0 |
0 |
T4 |
2160 |
0 |
0 |
0 |
T5 |
4991 |
0 |
0 |
0 |
T9 |
0 |
68 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
124 |
0 |
0 |
T16 |
1469 |
0 |
0 |
0 |
T17 |
1920 |
0 |
0 |
0 |
T18 |
7464 |
0 |
0 |
0 |
T19 |
2537 |
0 |
0 |
0 |
T20 |
6288 |
0 |
0 |
0 |
T21 |
1568 |
0 |
0 |
0 |
T28 |
0 |
41 |
0 |
0 |
T29 |
0 |
37 |
0 |
0 |
T30 |
0 |
28 |
0 |
0 |
T31 |
0 |
38 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T55,T58,T59 |
1 | 0 | Covered | T55,T58,T59 |
1 | 1 | Covered | T60,T113,T114 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T55,T58,T59 |
1 | 0 | Covered | T60,T113,T114 |
1 | 1 | Covered | T55,T58,T59 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151378284 |
38 |
0 |
0 |
T55 |
7936 |
1 |
0 |
0 |
T58 |
3454 |
1 |
0 |
0 |
T59 |
10680 |
1 |
0 |
0 |
T60 |
7675 |
4 |
0 |
0 |
T61 |
4898 |
1 |
0 |
0 |
T107 |
10139 |
1 |
0 |
0 |
T108 |
13490 |
1 |
0 |
0 |
T109 |
8919 |
1 |
0 |
0 |
T111 |
9052 |
1 |
0 |
0 |
T115 |
5478 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
530440499 |
38 |
0 |
0 |
T55 |
33122 |
1 |
0 |
0 |
T58 |
33159 |
1 |
0 |
0 |
T59 |
10355 |
1 |
0 |
0 |
T60 |
81868 |
4 |
0 |
0 |
T61 |
19591 |
1 |
0 |
0 |
T107 |
40556 |
1 |
0 |
0 |
T108 |
26430 |
1 |
0 |
0 |
T109 |
8919 |
1 |
0 |
0 |
T111 |
8690 |
1 |
0 |
0 |
T115 |
9739 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T54,T55,T58 |
1 | 0 | Covered | T54,T55,T58 |
1 | 1 | Covered | T61,T60,T113 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T54,T55,T58 |
1 | 0 | Covered | T61,T60,T113 |
1 | 1 | Covered | T54,T55,T58 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151378284 |
37 |
0 |
0 |
T54 |
8856 |
1 |
0 |
0 |
T55 |
7936 |
1 |
0 |
0 |
T58 |
3454 |
1 |
0 |
0 |
T60 |
7675 |
4 |
0 |
0 |
T61 |
4898 |
2 |
0 |
0 |
T107 |
10139 |
1 |
0 |
0 |
T109 |
8919 |
1 |
0 |
0 |
T111 |
9052 |
1 |
0 |
0 |
T115 |
5478 |
1 |
0 |
0 |
T116 |
6021 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
530440499 |
37 |
0 |
0 |
T54 |
17351 |
1 |
0 |
0 |
T55 |
33122 |
1 |
0 |
0 |
T58 |
33159 |
1 |
0 |
0 |
T60 |
81868 |
4 |
0 |
0 |
T61 |
19591 |
2 |
0 |
0 |
T107 |
40556 |
1 |
0 |
0 |
T109 |
8919 |
1 |
0 |
0 |
T111 |
8690 |
1 |
0 |
0 |
T115 |
9739 |
1 |
0 |
0 |
T116 |
27521 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T57,T54,T55 |
1 | 0 | Covered | T57,T54,T55 |
1 | 1 | Covered | T57,T58,T111 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T57,T54,T55 |
1 | 0 | Covered | T57,T58,T111 |
1 | 1 | Covered | T57,T54,T55 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151378284 |
34 |
0 |
0 |
T54 |
8856 |
2 |
0 |
0 |
T55 |
7936 |
1 |
0 |
0 |
T57 |
2252 |
2 |
0 |
0 |
T58 |
3454 |
2 |
0 |
0 |
T107 |
10139 |
2 |
0 |
0 |
T108 |
13490 |
1 |
0 |
0 |
T109 |
8919 |
1 |
0 |
0 |
T110 |
10562 |
3 |
0 |
0 |
T111 |
9052 |
3 |
0 |
0 |
T112 |
5889 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
264471396 |
34 |
0 |
0 |
T54 |
7947 |
2 |
0 |
0 |
T55 |
15757 |
1 |
0 |
0 |
T57 |
10393 |
2 |
0 |
0 |
T58 |
15980 |
2 |
0 |
0 |
T107 |
19539 |
2 |
0 |
0 |
T108 |
12639 |
1 |
0 |
0 |
T109 |
3678 |
1 |
0 |
0 |
T110 |
4276 |
3 |
0 |
0 |
T111 |
3544 |
3 |
0 |
0 |
T112 |
10280 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T56,T57,T54 |
1 | 0 | Covered | T56,T57,T54 |
1 | 1 | Covered | T57,T58,T111 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T56,T57,T54 |
1 | 0 | Covered | T57,T58,T111 |
1 | 1 | Covered | T56,T57,T54 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151378284 |
40 |
0 |
0 |
T54 |
8856 |
1 |
0 |
0 |
T55 |
7936 |
3 |
0 |
0 |
T56 |
9169 |
1 |
0 |
0 |
T57 |
2252 |
2 |
0 |
0 |
T58 |
3454 |
2 |
0 |
0 |
T59 |
10680 |
1 |
0 |
0 |
T107 |
10139 |
2 |
0 |
0 |
T108 |
13490 |
1 |
0 |
0 |
T109 |
8919 |
3 |
0 |
0 |
T110 |
10562 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
264471396 |
40 |
0 |
0 |
T54 |
7947 |
1 |
0 |
0 |
T55 |
15757 |
3 |
0 |
0 |
T56 |
3932 |
1 |
0 |
0 |
T57 |
10393 |
2 |
0 |
0 |
T58 |
15980 |
2 |
0 |
0 |
T59 |
4307 |
1 |
0 |
0 |
T107 |
19539 |
2 |
0 |
0 |
T108 |
12639 |
1 |
0 |
0 |
T109 |
3678 |
3 |
0 |
0 |
T110 |
4276 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T53,T54,T62 |
1 | 0 | Covered | T53,T54,T62 |
1 | 1 | Covered | T59,T112,T117 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T53,T54,T62 |
1 | 0 | Covered | T59,T112,T117 |
1 | 1 | Covered | T53,T54,T62 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151378284 |
33 |
0 |
0 |
T53 |
11556 |
1 |
0 |
0 |
T54 |
8856 |
3 |
0 |
0 |
T55 |
7936 |
1 |
0 |
0 |
T59 |
10680 |
4 |
0 |
0 |
T60 |
7675 |
1 |
0 |
0 |
T62 |
6081 |
1 |
0 |
0 |
T110 |
10562 |
3 |
0 |
0 |
T111 |
9052 |
1 |
0 |
0 |
T116 |
6021 |
1 |
0 |
0 |
T118 |
8480 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
132235143 |
33 |
0 |
0 |
T53 |
10678 |
1 |
0 |
0 |
T54 |
3973 |
3 |
0 |
0 |
T55 |
7879 |
1 |
0 |
0 |
T59 |
2152 |
4 |
0 |
0 |
T60 |
19913 |
1 |
0 |
0 |
T62 |
9498 |
1 |
0 |
0 |
T110 |
2140 |
3 |
0 |
0 |
T111 |
1772 |
1 |
0 |
0 |
T116 |
6372 |
1 |
0 |
0 |
T118 |
3910 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T54,T62,T55 |
1 | 0 | Covered | T54,T62,T55 |
1 | 1 | Covered | T59,T116,T117 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T54,T62,T55 |
1 | 0 | Covered | T59,T116,T117 |
1 | 1 | Covered | T54,T62,T55 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151378284 |
34 |
0 |
0 |
T54 |
8856 |
3 |
0 |
0 |
T55 |
7936 |
1 |
0 |
0 |
T59 |
10680 |
4 |
0 |
0 |
T60 |
7675 |
1 |
0 |
0 |
T61 |
4898 |
1 |
0 |
0 |
T62 |
6081 |
1 |
0 |
0 |
T108 |
13490 |
2 |
0 |
0 |
T110 |
10562 |
2 |
0 |
0 |
T116 |
6021 |
2 |
0 |
0 |
T118 |
8480 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
132235143 |
34 |
0 |
0 |
T54 |
3973 |
3 |
0 |
0 |
T55 |
7879 |
1 |
0 |
0 |
T59 |
2152 |
4 |
0 |
0 |
T60 |
19913 |
1 |
0 |
0 |
T61 |
4680 |
1 |
0 |
0 |
T62 |
9498 |
1 |
0 |
0 |
T108 |
6319 |
2 |
0 |
0 |
T110 |
2140 |
2 |
0 |
0 |
T116 |
6372 |
2 |
0 |
0 |
T118 |
3910 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T56,T53,T57 |
1 | 0 | Covered | T56,T53,T57 |
1 | 1 | Covered | T57,T55,T58 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T56,T53,T57 |
1 | 0 | Covered | T57,T55,T58 |
1 | 1 | Covered | T56,T53,T57 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151378284 |
32 |
0 |
0 |
T53 |
11556 |
1 |
0 |
0 |
T54 |
8856 |
1 |
0 |
0 |
T55 |
7936 |
2 |
0 |
0 |
T56 |
9169 |
1 |
0 |
0 |
T57 |
2252 |
3 |
0 |
0 |
T58 |
3454 |
2 |
0 |
0 |
T60 |
7675 |
1 |
0 |
0 |
T107 |
10139 |
2 |
0 |
0 |
T109 |
8919 |
2 |
0 |
0 |
T119 |
3442 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
563145299 |
32 |
0 |
0 |
T53 |
46224 |
1 |
0 |
0 |
T54 |
18074 |
1 |
0 |
0 |
T55 |
34504 |
2 |
0 |
0 |
T56 |
9169 |
1 |
0 |
0 |
T57 |
22529 |
3 |
0 |
0 |
T58 |
34542 |
2 |
0 |
0 |
T60 |
85282 |
1 |
0 |
0 |
T107 |
42247 |
2 |
0 |
0 |
T109 |
9291 |
2 |
0 |
0 |
T119 |
14344 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T56,T53,T57 |
1 | 0 | Covered | T56,T53,T57 |
1 | 1 | Covered | T53,T57,T107 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T56,T53,T57 |
1 | 0 | Covered | T53,T57,T107 |
1 | 1 | Covered | T56,T53,T57 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151378284 |
29 |
0 |
0 |
T53 |
11556 |
2 |
0 |
0 |
T54 |
8856 |
2 |
0 |
0 |
T56 |
9169 |
1 |
0 |
0 |
T57 |
2252 |
2 |
0 |
0 |
T58 |
3454 |
1 |
0 |
0 |
T60 |
7675 |
1 |
0 |
0 |
T107 |
10139 |
3 |
0 |
0 |
T109 |
8919 |
2 |
0 |
0 |
T119 |
3442 |
1 |
0 |
0 |
T120 |
7334 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
563145299 |
29 |
0 |
0 |
T53 |
46224 |
2 |
0 |
0 |
T54 |
18074 |
2 |
0 |
0 |
T56 |
9169 |
1 |
0 |
0 |
T57 |
22529 |
2 |
0 |
0 |
T58 |
34542 |
1 |
0 |
0 |
T60 |
85282 |
1 |
0 |
0 |
T107 |
42247 |
3 |
0 |
0 |
T109 |
9291 |
2 |
0 |
0 |
T119 |
14344 |
1 |
0 |
0 |
T120 |
7484 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T53,T57,T54 |
1 | 0 | Covered | T53,T57,T54 |
1 | 1 | Covered | T53,T111,T112 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T53,T57,T54 |
1 | 0 | Covered | T53,T111,T112 |
1 | 1 | Covered | T53,T57,T54 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151378284 |
36 |
0 |
0 |
T53 |
11556 |
2 |
0 |
0 |
T54 |
8856 |
3 |
0 |
0 |
T57 |
2252 |
1 |
0 |
0 |
T59 |
10680 |
1 |
0 |
0 |
T60 |
7675 |
1 |
0 |
0 |
T61 |
4898 |
1 |
0 |
0 |
T62 |
6081 |
1 |
0 |
0 |
T107 |
10139 |
1 |
0 |
0 |
T108 |
13490 |
1 |
0 |
0 |
T109 |
8919 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
270067595 |
36 |
0 |
0 |
T53 |
22188 |
2 |
0 |
0 |
T54 |
8676 |
3 |
0 |
0 |
T57 |
10814 |
1 |
0 |
0 |
T59 |
5178 |
1 |
0 |
0 |
T60 |
40936 |
1 |
0 |
0 |
T61 |
9796 |
1 |
0 |
0 |
T62 |
19460 |
1 |
0 |
0 |
T107 |
20279 |
1 |
0 |
0 |
T108 |
13215 |
1 |
0 |
0 |
T109 |
4459 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T56,T57,T54 |
1 | 0 | Covered | T56,T57,T54 |
1 | 1 | Covered | T54,T111,T112 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T56,T57,T54 |
1 | 0 | Covered | T54,T111,T112 |
1 | 1 | Covered | T56,T57,T54 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151378284 |
37 |
0 |
0 |
T54 |
8856 |
3 |
0 |
0 |
T56 |
9169 |
1 |
0 |
0 |
T57 |
2252 |
2 |
0 |
0 |
T59 |
10680 |
2 |
0 |
0 |
T60 |
7675 |
1 |
0 |
0 |
T62 |
6081 |
1 |
0 |
0 |
T107 |
10139 |
1 |
0 |
0 |
T108 |
13490 |
1 |
0 |
0 |
T109 |
8919 |
2 |
0 |
0 |
T111 |
9052 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
270067595 |
37 |
0 |
0 |
T54 |
8676 |
3 |
0 |
0 |
T56 |
4401 |
1 |
0 |
0 |
T57 |
10814 |
2 |
0 |
0 |
T59 |
5178 |
2 |
0 |
0 |
T60 |
40936 |
1 |
0 |
0 |
T62 |
19460 |
1 |
0 |
0 |
T107 |
20279 |
1 |
0 |
0 |
T108 |
13215 |
1 |
0 |
0 |
T109 |
4459 |
2 |
0 |
0 |
T111 |
4345 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
527839865 |
95217 |
0 |
0 |
T1 |
161508 |
1782 |
0 |
0 |
T2 |
591259 |
401 |
0 |
0 |
T3 |
0 |
218 |
0 |
0 |
T4 |
4318 |
0 |
0 |
0 |
T5 |
9981 |
0 |
0 |
0 |
T9 |
0 |
224 |
0 |
0 |
T10 |
0 |
32 |
0 |
0 |
T11 |
0 |
514 |
0 |
0 |
T12 |
0 |
35 |
0 |
0 |
T16 |
2939 |
0 |
0 |
0 |
T17 |
3840 |
0 |
0 |
0 |
T18 |
14927 |
0 |
0 |
0 |
T19 |
5075 |
0 |
0 |
0 |
T20 |
12577 |
0 |
0 |
0 |
T21 |
3136 |
0 |
0 |
0 |
T30 |
0 |
157 |
0 |
0 |
T31 |
0 |
225 |
0 |
0 |
T73 |
0 |
19 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22387257 |
94635 |
0 |
0 |
T1 |
721579 |
1782 |
0 |
0 |
T2 |
1784 |
401 |
0 |
0 |
T3 |
0 |
218 |
0 |
0 |
T4 |
314 |
0 |
0 |
0 |
T5 |
727 |
0 |
0 |
0 |
T9 |
0 |
224 |
0 |
0 |
T10 |
0 |
32 |
0 |
0 |
T11 |
0 |
514 |
0 |
0 |
T12 |
0 |
35 |
0 |
0 |
T16 |
214 |
0 |
0 |
0 |
T17 |
280 |
0 |
0 |
0 |
T18 |
1088 |
0 |
0 |
0 |
T19 |
370 |
0 |
0 |
0 |
T20 |
916 |
0 |
0 |
0 |
T21 |
228 |
0 |
0 |
0 |
T30 |
0 |
157 |
0 |
0 |
T31 |
0 |
225 |
0 |
0 |
T73 |
0 |
19 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
263218881 |
93829 |
0 |
0 |
T1 |
807368 |
1782 |
0 |
0 |
T2 |
295379 |
401 |
0 |
0 |
T3 |
0 |
216 |
0 |
0 |
T4 |
2444 |
0 |
0 |
0 |
T5 |
5999 |
0 |
0 |
0 |
T9 |
0 |
224 |
0 |
0 |
T10 |
0 |
32 |
0 |
0 |
T11 |
0 |
514 |
0 |
0 |
T12 |
0 |
35 |
0 |
0 |
T16 |
1457 |
0 |
0 |
0 |
T17 |
2107 |
0 |
0 |
0 |
T18 |
7437 |
0 |
0 |
0 |
T19 |
2504 |
0 |
0 |
0 |
T20 |
6235 |
0 |
0 |
0 |
T21 |
1549 |
0 |
0 |
0 |
T30 |
0 |
157 |
0 |
0 |
T31 |
0 |
225 |
0 |
0 |
T73 |
0 |
19 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22387257 |
93255 |
0 |
0 |
T1 |
721579 |
1782 |
0 |
0 |
T2 |
1784 |
401 |
0 |
0 |
T3 |
0 |
216 |
0 |
0 |
T4 |
314 |
0 |
0 |
0 |
T5 |
727 |
0 |
0 |
0 |
T9 |
0 |
224 |
0 |
0 |
T10 |
0 |
32 |
0 |
0 |
T11 |
0 |
514 |
0 |
0 |
T12 |
0 |
35 |
0 |
0 |
T16 |
214 |
0 |
0 |
0 |
T17 |
280 |
0 |
0 |
0 |
T18 |
1088 |
0 |
0 |
0 |
T19 |
370 |
0 |
0 |
0 |
T20 |
916 |
0 |
0 |
0 |
T21 |
228 |
0 |
0 |
0 |
T30 |
0 |
157 |
0 |
0 |
T31 |
0 |
225 |
0 |
0 |
T73 |
0 |
19 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
131608875 |
92178 |
0 |
0 |
T1 |
403682 |
1782 |
0 |
0 |
T2 |
147690 |
401 |
0 |
0 |
T3 |
0 |
203 |
0 |
0 |
T4 |
1221 |
0 |
0 |
0 |
T5 |
2999 |
0 |
0 |
0 |
T9 |
0 |
224 |
0 |
0 |
T10 |
0 |
32 |
0 |
0 |
T11 |
0 |
514 |
0 |
0 |
T12 |
0 |
35 |
0 |
0 |
T16 |
729 |
0 |
0 |
0 |
T17 |
1053 |
0 |
0 |
0 |
T18 |
3719 |
0 |
0 |
0 |
T19 |
1252 |
0 |
0 |
0 |
T20 |
3117 |
0 |
0 |
0 |
T21 |
774 |
0 |
0 |
0 |
T30 |
0 |
157 |
0 |
0 |
T31 |
0 |
225 |
0 |
0 |
T73 |
0 |
19 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22387257 |
91610 |
0 |
0 |
T1 |
721579 |
1782 |
0 |
0 |
T2 |
1784 |
401 |
0 |
0 |
T3 |
0 |
203 |
0 |
0 |
T4 |
314 |
0 |
0 |
0 |
T5 |
727 |
0 |
0 |
0 |
T9 |
0 |
224 |
0 |
0 |
T10 |
0 |
32 |
0 |
0 |
T11 |
0 |
514 |
0 |
0 |
T12 |
0 |
35 |
0 |
0 |
T16 |
214 |
0 |
0 |
0 |
T17 |
280 |
0 |
0 |
0 |
T18 |
1088 |
0 |
0 |
0 |
T19 |
370 |
0 |
0 |
0 |
T20 |
916 |
0 |
0 |
0 |
T21 |
228 |
0 |
0 |
0 |
T30 |
0 |
157 |
0 |
0 |
T31 |
0 |
225 |
0 |
0 |
T73 |
0 |
19 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
560436205 |
111349 |
0 |
0 |
T1 |
170943 |
2319 |
0 |
0 |
T2 |
669915 |
509 |
0 |
0 |
T3 |
0 |
193 |
0 |
0 |
T4 |
4499 |
0 |
0 |
0 |
T5 |
10398 |
0 |
0 |
0 |
T9 |
0 |
344 |
0 |
0 |
T10 |
0 |
32 |
0 |
0 |
T11 |
0 |
622 |
0 |
0 |
T12 |
0 |
35 |
0 |
0 |
T16 |
3062 |
0 |
0 |
0 |
T17 |
4000 |
0 |
0 |
0 |
T18 |
15549 |
0 |
0 |
0 |
T19 |
5286 |
0 |
0 |
0 |
T20 |
13101 |
0 |
0 |
0 |
T21 |
3266 |
0 |
0 |
0 |
T30 |
0 |
205 |
0 |
0 |
T31 |
0 |
261 |
0 |
0 |
T73 |
0 |
31 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22478607 |
111035 |
0 |
0 |
T1 |
722119 |
2319 |
0 |
0 |
T2 |
1892 |
509 |
0 |
0 |
T3 |
0 |
193 |
0 |
0 |
T4 |
314 |
0 |
0 |
0 |
T5 |
727 |
0 |
0 |
0 |
T9 |
0 |
344 |
0 |
0 |
T10 |
0 |
32 |
0 |
0 |
T11 |
0 |
622 |
0 |
0 |
T12 |
0 |
35 |
0 |
0 |
T16 |
214 |
0 |
0 |
0 |
T17 |
280 |
0 |
0 |
0 |
T18 |
1088 |
0 |
0 |
0 |
T19 |
370 |
0 |
0 |
0 |
T20 |
916 |
0 |
0 |
0 |
T21 |
228 |
0 |
0 |
0 |
T30 |
0 |
205 |
0 |
0 |
T31 |
0 |
261 |
0 |
0 |
T73 |
0 |
31 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
268767264 |
108470 |
0 |
0 |
T1 |
817662 |
2198 |
0 |
0 |
T2 |
318685 |
497 |
0 |
0 |
T3 |
0 |
184 |
0 |
0 |
T4 |
2160 |
0 |
0 |
0 |
T5 |
4991 |
0 |
0 |
0 |
T9 |
0 |
344 |
0 |
0 |
T10 |
0 |
32 |
0 |
0 |
T11 |
0 |
610 |
0 |
0 |
T12 |
0 |
35 |
0 |
0 |
T16 |
1469 |
0 |
0 |
0 |
T17 |
1920 |
0 |
0 |
0 |
T18 |
7464 |
0 |
0 |
0 |
T19 |
2537 |
0 |
0 |
0 |
T20 |
6288 |
0 |
0 |
0 |
T21 |
1568 |
0 |
0 |
0 |
T30 |
0 |
189 |
0 |
0 |
T31 |
0 |
261 |
0 |
0 |
T73 |
0 |
19 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22285778 |
107582 |
0 |
0 |
T1 |
721999 |
2198 |
0 |
0 |
T2 |
1880 |
497 |
0 |
0 |
T3 |
0 |
184 |
0 |
0 |
T4 |
314 |
0 |
0 |
0 |
T5 |
727 |
0 |
0 |
0 |
T9 |
0 |
344 |
0 |
0 |
T10 |
0 |
32 |
0 |
0 |
T11 |
0 |
610 |
0 |
0 |
T12 |
0 |
35 |
0 |
0 |
T16 |
214 |
0 |
0 |
0 |
T17 |
280 |
0 |
0 |
0 |
T18 |
1088 |
0 |
0 |
0 |
T19 |
370 |
0 |
0 |
0 |
T20 |
916 |
0 |
0 |
0 |
T21 |
228 |
0 |
0 |
0 |
T30 |
0 |
189 |
0 |
0 |
T31 |
0 |
261 |
0 |
0 |
T73 |
0 |
19 |
0 |
0 |