Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	151378284	4767668	0	0
clk_enables_rd_A	151378284	52592	0	0
clk_hints_rd_A	151378284	46746	0	0
extclk_ctrl_rd_A	151378284	61245	0	0
extclk_ctrl_regwen_rd_A	151378284	45692	0	0
jitter_enable_rd_A	151378284	68803	0	0
jitter_regwen_rd_A	151378284	51373	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151378284	4767668	0	0
T1	429309	211006	0	0
T2	660377	0	0	0
T3	0	54168	0	0
T4	2160	0	0	0
T5	2495	0	0	0
T16	1899	0	0	0
T17	1879	0	0	0
T18	2021	0	0	0
T19	898	0	0	0
T20	3274	0	0	0
T21	3266	0	0	0
T24	0	61257	0	0
T25	0	47034	0	0
T27	0	62304	0	0
T63	0	140625	0	0
T64	0	104857	0	0
T65	0	40143	0	0
T66	0	111943	0	0
T67	0	113397	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151378284	52592	0	0
T2	660377	15	0	0
T3	162902	1059	0	0
T20	3274	0	0	0
T21	3266	0	0	0
T24	0	2199	0	0
T25	0	1896	0	0
T27	0	2180	0	0
T28	36824	0	0	0
T66	0	4743	0	0
T68	1270	0	0	0
T69	3623	0	0	0
T70	826	0	0	0
T71	1518	0	0	0
T72	2741	0	0	0
T121	0	6	0	0
T122	0	6	0	0
T123	0	5	0	0
T124	0	1	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151378284	46746	0	0
T2	660377	19	0	0
T3	162902	1086	0	0
T20	3274	0	0	0
T21	3266	0	0	0
T24	0	1979	0	0
T25	0	1673	0	0
T27	0	2034	0	0
T28	36824	0	0	0
T66	0	3934	0	0
T68	1270	0	0	0
T69	3623	0	0	0
T70	826	0	0	0
T71	1518	0	0	0
T72	2741	0	0	0
T121	0	2	0	0
T122	0	4	0	0
T123	0	3	0	0
T124	0	2	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151378284	61245	0	0
T2	660377	7	0	0
T3	162902	1296	0	0
T5	2495	62	0	0
T16	1899	0	0	0
T17	1879	0	0	0
T18	2021	0	0	0
T19	898	0	0	0
T20	3274	0	0	0
T21	3266	0	0	0
T47	0	55	0	0
T68	1270	0	0	0
T72	0	43	0	0
T102	0	4	0	0
T125	0	77	0	0
T126	0	56	0	0
T127	0	58	0	0
T128	0	28	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151378284	45692	0	0
T3	162902	1031	0	0
T9	394695	0	0	0
T24	0	2158	0	0
T25	0	1665	0	0
T27	0	2042	0	0
T28	36824	0	0	0
T48	0	47	0	0
T66	0	4021	0	0
T68	1270	0	0	0
T69	3623	0	0	0
T70	826	0	0	0
T71	1518	0	0	0
T72	2741	0	0	0
T100	0	25	0	0
T102	1287	0	0	0
T125	2919	0	0	0
T129	0	2133	0	0
T130	0	2489	0	0
T131	0	36	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151378284	68803	0	0
T2	660377	423	0	0
T3	162902	1303	0	0
T20	3274	0	0	0
T21	3266	0	0	0
T24	0	3636	0	0
T25	0	2317	0	0
T27	0	3038	0	0
T28	36824	0	0	0
T66	0	6187	0	0
T68	1270	0	0	0
T69	3623	0	0	0
T70	826	0	0	0
T71	1518	0	0	0
T72	2741	0	0	0
T121	0	87	0	0
T122	0	109	0	0
T123	0	123	0	0
T124	0	112	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151378284	51373	0	0
T3	162902	1170	0	0
T9	394695	0	0	0
T24	0	2247	0	0
T25	0	1704	0	0
T27	0	2274	0	0
T28	36824	0	0	0
T66	0	4354	0	0
T68	1270	0	0	0
T69	3623	0	0	0
T70	826	0	0	0
T71	1518	0	0	0
T72	2741	0	0	0
T102	1287	0	0	0
T125	2919	0	0	0
T129	0	2316	0	0
T130	0	3020	0	0
T132	0	4402	0	0
T133	0	5163	0	0
T134	0	533	0	0