SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.clkmgr_div2_sva_if | 100.00 | 100.00 | 100.00 | 100.00 | |||
tb.dut.clkmgr_div4_sva_if | 100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.65 | 100.00 | 93.24 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.65 | 100.00 | 93.24 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T1,T4,T5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div2.Div2Stepped_A | 527840298 | 4357 | 0 | 0 |
g_div2.Div2Whole_A | 527840298 | 5127 | 0 | 0 |
g_div4.Div4Stepped_A | 263219293 | 4287 | 0 | 0 |
g_div4.Div4Whole_A | 263219293 | 4858 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 527840298 | 4357 | 0 | 0 |
T1 | 161508 | 91 | 0 | 0 |
T2 | 591260 | 1 | 0 | 0 |
T3 | 0 | 37 | 0 | 0 |
T4 | 4319 | 9 | 0 | 0 |
T5 | 9982 | 12 | 0 | 0 |
T9 | 0 | 7 | 0 | 0 |
T16 | 2940 | 0 | 0 | 0 |
T17 | 3841 | 5 | 0 | 0 |
T18 | 14928 | 0 | 0 | 0 |
T19 | 5076 | 0 | 0 | 0 |
T20 | 12577 | 0 | 0 | 0 |
T21 | 3137 | 0 | 0 | 0 |
T71 | 0 | 5 | 0 | 0 |
T72 | 0 | 6 | 0 | 0 |
T102 | 0 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 527840298 | 5127 | 0 | 0 |
T1 | 161508 | 111 | 0 | 0 |
T2 | 591260 | 2 | 0 | 0 |
T3 | 0 | 40 | 0 | 0 |
T4 | 4319 | 10 | 0 | 0 |
T5 | 9982 | 11 | 0 | 0 |
T9 | 0 | 8 | 0 | 0 |
T16 | 2940 | 0 | 0 | 0 |
T17 | 3841 | 7 | 0 | 0 |
T18 | 14928 | 0 | 0 | 0 |
T19 | 5076 | 0 | 0 | 0 |
T20 | 12577 | 0 | 0 | 0 |
T21 | 3137 | 0 | 0 | 0 |
T71 | 0 | 5 | 0 | 0 |
T72 | 0 | 10 | 0 | 0 |
T102 | 0 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 263219293 | 4287 | 0 | 0 |
T1 | 807368 | 91 | 0 | 0 |
T2 | 295379 | 0 | 0 | 0 |
T3 | 0 | 37 | 0 | 0 |
T4 | 2444 | 9 | 0 | 0 |
T5 | 6000 | 12 | 0 | 0 |
T9 | 0 | 6 | 0 | 0 |
T16 | 1458 | 0 | 0 | 0 |
T17 | 2107 | 5 | 0 | 0 |
T18 | 7438 | 0 | 0 | 0 |
T19 | 2505 | 0 | 0 | 0 |
T20 | 6235 | 0 | 0 | 0 |
T21 | 1549 | 0 | 0 | 0 |
T71 | 0 | 5 | 0 | 0 |
T72 | 0 | 6 | 0 | 0 |
T102 | 0 | 1 | 0 | 0 |
T125 | 0 | 5 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 263219293 | 4858 | 0 | 0 |
T1 | 807368 | 109 | 0 | 0 |
T2 | 295379 | 2 | 0 | 0 |
T3 | 0 | 40 | 0 | 0 |
T4 | 2444 | 10 | 0 | 0 |
T5 | 6000 | 11 | 0 | 0 |
T9 | 0 | 6 | 0 | 0 |
T16 | 1458 | 0 | 0 | 0 |
T17 | 2107 | 7 | 0 | 0 |
T18 | 7438 | 0 | 0 | 0 |
T19 | 2505 | 0 | 0 | 0 |
T20 | 6235 | 0 | 0 | 0 |
T21 | 1549 | 0 | 0 | 0 |
T71 | 0 | 5 | 0 | 0 |
T72 | 0 | 10 | 0 | 0 |
T102 | 0 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T1,T4,T5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div2.Div2Stepped_A | 527840298 | 4357 | 0 | 0 |
g_div2.Div2Whole_A | 527840298 | 5127 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 527840298 | 4357 | 0 | 0 |
T1 | 161508 | 91 | 0 | 0 |
T2 | 591260 | 1 | 0 | 0 |
T3 | 0 | 37 | 0 | 0 |
T4 | 4319 | 9 | 0 | 0 |
T5 | 9982 | 12 | 0 | 0 |
T9 | 0 | 7 | 0 | 0 |
T16 | 2940 | 0 | 0 | 0 |
T17 | 3841 | 5 | 0 | 0 |
T18 | 14928 | 0 | 0 | 0 |
T19 | 5076 | 0 | 0 | 0 |
T20 | 12577 | 0 | 0 | 0 |
T21 | 3137 | 0 | 0 | 0 |
T71 | 0 | 5 | 0 | 0 |
T72 | 0 | 6 | 0 | 0 |
T102 | 0 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 527840298 | 5127 | 0 | 0 |
T1 | 161508 | 111 | 0 | 0 |
T2 | 591260 | 2 | 0 | 0 |
T3 | 0 | 40 | 0 | 0 |
T4 | 4319 | 10 | 0 | 0 |
T5 | 9982 | 11 | 0 | 0 |
T9 | 0 | 8 | 0 | 0 |
T16 | 2940 | 0 | 0 | 0 |
T17 | 3841 | 7 | 0 | 0 |
T18 | 14928 | 0 | 0 | 0 |
T19 | 5076 | 0 | 0 | 0 |
T20 | 12577 | 0 | 0 | 0 |
T21 | 3137 | 0 | 0 | 0 |
T71 | 0 | 5 | 0 | 0 |
T72 | 0 | 10 | 0 | 0 |
T102 | 0 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T1,T4,T5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div4.Div4Stepped_A | 263219293 | 4287 | 0 | 0 |
g_div4.Div4Whole_A | 263219293 | 4858 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 263219293 | 4287 | 0 | 0 |
T1 | 807368 | 91 | 0 | 0 |
T2 | 295379 | 0 | 0 | 0 |
T3 | 0 | 37 | 0 | 0 |
T4 | 2444 | 9 | 0 | 0 |
T5 | 6000 | 12 | 0 | 0 |
T9 | 0 | 6 | 0 | 0 |
T16 | 1458 | 0 | 0 | 0 |
T17 | 2107 | 5 | 0 | 0 |
T18 | 7438 | 0 | 0 | 0 |
T19 | 2505 | 0 | 0 | 0 |
T20 | 6235 | 0 | 0 | 0 |
T21 | 1549 | 0 | 0 | 0 |
T71 | 0 | 5 | 0 | 0 |
T72 | 0 | 6 | 0 | 0 |
T102 | 0 | 1 | 0 | 0 |
T125 | 0 | 5 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 263219293 | 4858 | 0 | 0 |
T1 | 807368 | 109 | 0 | 0 |
T2 | 295379 | 2 | 0 | 0 |
T3 | 0 | 40 | 0 | 0 |
T4 | 2444 | 10 | 0 | 0 |
T5 | 6000 | 11 | 0 | 0 |
T9 | 0 | 6 | 0 | 0 |
T16 | 1458 | 0 | 0 | 0 |
T17 | 2107 | 7 | 0 | 0 |
T18 | 7438 | 0 | 0 | 0 |
T19 | 2505 | 0 | 0 | 0 |
T20 | 6235 | 0 | 0 | 0 |
T21 | 1549 | 0 | 0 | 0 |
T71 | 0 | 5 | 0 | 0 |
T72 | 0 | 10 | 0 | 0 |
T102 | 0 | 1 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |