Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	451336311	354	0	0
StatusRise_A	451336311	354	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	451336311	354	0	0
T10	274935	0	0	0
T29	195675	0	0	0
T37	2128	2	0	0
T38	4419	10	0	0
T39	0	4	0	0
T41	0	5	0	0
T121	1590	0	0	0
T127	7680	0	0	0
T135	0	14	0	0
T136	0	8	0	0
T137	0	6	0	0
T138	0	10	0	0
T139	0	5	0	0
T140	0	12	0	0
T141	0	1	0	0
T142	5178	0	0	0
T143	6897	0	0	0
T144	2511	0	0	0
T145	6414	0	0	0
T146	3714	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	451336311	354	0	0
T10	274935	0	0	0
T29	195675	0	0	0
T37	2128	2	0	0
T38	4419	10	0	0
T39	0	4	0	0
T41	0	5	0	0
T121	1590	0	0	0
T127	7680	0	0	0
T135	0	14	0	0
T136	0	8	0	0
T137	0	6	0	0
T138	0	10	0	0
T139	0	5	0	0
T140	0	12	0	0
T141	0	1	0	0
T142	5178	0	0	0
T143	6897	0	0	0
T144	2511	0	0	0
T145	6414	0	0	0
T146	3714	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	150445437	118	0	0
StatusRise_A	150445437	118	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150445437	118	0	0
T10	91645	0	0	0
T29	65225	0	0	0
T38	1473	4	0	0
T39	0	1	0	0
T41	0	2	0	0
T121	1590	0	0	0
T127	2560	0	0	0
T135	0	4	0	0
T136	0	3	0	0
T137	0	2	0	0
T138	0	2	0	0
T139	0	1	0	0
T140	0	5	0	0
T141	0	1	0	0
T142	1726	0	0	0
T143	2299	0	0	0
T144	837	0	0	0
T145	2138	0	0	0
T146	1238	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150445437	118	0	0
T10	91645	0	0	0
T29	65225	0	0	0
T38	1473	4	0	0
T39	0	1	0	0
T41	0	2	0	0
T121	1590	0	0	0
T127	2560	0	0	0
T135	0	4	0	0
T136	0	3	0	0
T137	0	2	0	0
T138	0	2	0	0
T139	0	1	0	0
T140	0	5	0	0
T141	0	1	0	0
T142	1726	0	0	0
T143	2299	0	0	0
T144	837	0	0	0
T145	2138	0	0	0
T146	1238	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	150445437	124	0	0
StatusRise_A	150445437	124	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150445437	124	0	0
T10	91645	0	0	0
T29	65225	0	0	0
T37	1064	1	0	0
T38	1473	2	0	0
T39	0	2	0	0
T41	0	2	0	0
T127	2560	0	0	0
T135	0	5	0	0
T136	0	3	0	0
T137	0	2	0	0
T138	0	4	0	0
T139	0	2	0	0
T140	0	4	0	0
T142	1726	0	0	0
T143	2299	0	0	0
T144	837	0	0	0
T145	2138	0	0	0
T146	1238	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150445437	124	0	0
T10	91645	0	0	0
T29	65225	0	0	0
T37	1064	1	0	0
T38	1473	2	0	0
T39	0	2	0	0
T41	0	2	0	0
T127	2560	0	0	0
T135	0	5	0	0
T136	0	3	0	0
T137	0	2	0	0
T138	0	4	0	0
T139	0	2	0	0
T140	0	4	0	0
T142	1726	0	0	0
T143	2299	0	0	0
T144	837	0	0	0
T145	2138	0	0	0
T146	1238	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	150445437	112	0	0
StatusRise_A	150445437	112	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150445437	112	0	0
T10	91645	0	0	0
T29	65225	0	0	0
T37	1064	1	0	0
T38	1473	4	0	0
T39	0	1	0	0
T41	0	1	0	0
T127	2560	0	0	0
T135	0	5	0	0
T136	0	2	0	0
T137	0	2	0	0
T138	0	4	0	0
T139	0	2	0	0
T140	0	3	0	0
T142	1726	0	0	0
T143	2299	0	0	0
T144	837	0	0	0
T145	2138	0	0	0
T146	1238	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150445437	112	0	0
T10	91645	0	0	0
T29	65225	0	0	0
T37	1064	1	0	0
T38	1473	4	0	0
T39	0	1	0	0
T41	0	1	0	0
T127	2560	0	0	0
T135	0	5	0	0
T136	0	2	0	0
T137	0	2	0	0
T138	0	4	0	0
T139	0	2	0	0
T140	0	3	0	0
T142	1726	0	0	0
T143	2299	0	0	0
T144	837	0	0	0
T145	2138	0	0	0
T146	1238	0	0	0