Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	47438	0	0
CgEnOn_A	2147483647	37939	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	47438	0	0
T1	1714444	524	0	0
T2	2374158	33	0	0
T3	0	14	0	0
T4	16981	3	0	0
T5	39775	3	0	0
T10	289564	0	0	0
T16	11249	6	0	0
T17	15000	3	0	0
T18	57181	10	0	0
T19	19403	27	0	0
T20	48131	13	0	0
T21	11991	14	0	0
T29	173621	0	0	0
T37	4413	5	0	0
T38	4160	10	0	0
T39	0	10	0	0
T41	0	10	0	0
T121	7229	0	0	0
T127	49746	0	0	0
T135	0	25	0	0
T136	0	15	0	0
T137	0	10	0	0
T138	0	20	0	0
T139	0	10	0	0
T140	0	20	0	0
T142	27894	0	0	0
T143	14691	0	0	0
T144	10090	0	0	0
T145	6962	0	0	0
T146	17640	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	37939	0	0
T1	1714444	494	0	0
T2	2374158	15	0	0
T3	0	96	0	0
T4	16981	0	0	0
T5	39775	0	0	0
T9	0	74	0	0
T10	289564	0	0	0
T16	11249	3	0	0
T17	15000	0	0	0
T18	57181	7	0	0
T19	19403	24	0	0
T20	48131	10	0	0
T21	11991	0	0	0
T29	173621	0	0	0
T37	4413	8	0	0
T38	4160	16	0	0
T39	0	10	0	0
T41	0	10	0	0
T68	0	4	0	0
T70	0	20	0	0
T121	7229	0	0	0
T127	49746	0	0	0
T135	0	25	0	0
T136	0	15	0	0
T137	0	10	0	0
T138	0	20	0	0
T139	0	10	0	0
T140	0	20	0	0
T142	27894	0	0	0
T143	14691	0	0	0
T144	10090	0	0	0
T145	6962	0	0	0
T146	17640	0	0	0
T147	0	14	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	263218881	130	0	0
CgEnOn_A	263218881	130	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	263218881	130	0	0
T10	43977	0	0	0
T29	17268	0	0	0
T37	954	1	0	0
T38	585	2	0	0
T39	0	2	0	0
T41	0	2	0	0
T127	8087	0	0	0
T135	0	5	0	0
T136	0	3	0	0
T137	0	2	0	0
T138	0	4	0	0
T139	0	2	0	0
T140	0	4	0	0
T142	4388	0	0	0
T143	2199	0	0	0
T144	1508	0	0	0
T145	1093	0	0	0
T146	2642	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	263218881	130	0	0
T10	43977	0	0	0
T29	17268	0	0	0
T37	954	1	0	0
T38	585	2	0	0
T39	0	2	0	0
T41	0	2	0	0
T127	8087	0	0	0
T135	0	5	0	0
T136	0	3	0	0
T137	0	2	0	0
T138	0	4	0	0
T139	0	2	0	0
T140	0	4	0	0
T142	4388	0	0	0
T143	2199	0	0	0
T144	1508	0	0	0
T145	1093	0	0	0
T146	2642	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	131608875	130	0	0
CgEnOn_A	131608875	130	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131608875	130	0	0
T10	21988	0	0	0
T29	8636	0	0	0
T37	477	1	0	0
T38	293	2	0	0
T39	0	2	0	0
T41	0	2	0	0
T127	4043	0	0	0
T135	0	5	0	0
T136	0	3	0	0
T137	0	2	0	0
T138	0	4	0	0
T139	0	2	0	0
T140	0	4	0	0
T142	2194	0	0	0
T143	1099	0	0	0
T144	754	0	0	0
T145	546	0	0	0
T146	1321	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131608875	130	0	0
T10	21988	0	0	0
T29	8636	0	0	0
T37	477	1	0	0
T38	293	2	0	0
T39	0	2	0	0
T41	0	2	0	0
T127	4043	0	0	0
T135	0	5	0	0
T136	0	3	0	0
T137	0	2	0	0
T138	0	4	0	0
T139	0	2	0	0
T140	0	4	0	0
T142	2194	0	0	0
T143	1099	0	0	0
T144	754	0	0	0
T145	546	0	0	0
T146	1321	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	131608875	130	0	0
CgEnOn_A	131608875	130	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131608875	130	0	0
T10	21988	0	0	0
T29	8636	0	0	0
T37	477	1	0	0
T38	293	2	0	0
T39	0	2	0	0
T41	0	2	0	0
T127	4043	0	0	0
T135	0	5	0	0
T136	0	3	0	0
T137	0	2	0	0
T138	0	4	0	0
T139	0	2	0	0
T140	0	4	0	0
T142	2194	0	0	0
T143	1099	0	0	0
T144	754	0	0	0
T145	546	0	0	0
T146	1321	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131608875	130	0	0
T10	21988	0	0	0
T29	8636	0	0	0
T37	477	1	0	0
T38	293	2	0	0
T39	0	2	0	0
T41	0	2	0	0
T127	4043	0	0	0
T135	0	5	0	0
T136	0	3	0	0
T137	0	2	0	0
T138	0	4	0	0
T139	0	2	0	0
T140	0	4	0	0
T142	2194	0	0	0
T143	1099	0	0	0
T144	754	0	0	0
T145	546	0	0	0
T146	1321	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	131608875	130	0	0
CgEnOn_A	131608875	130	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131608875	130	0	0
T10	21988	0	0	0
T29	8636	0	0	0
T37	477	1	0	0
T38	293	2	0	0
T39	0	2	0	0
T41	0	2	0	0
T127	4043	0	0	0
T135	0	5	0	0
T136	0	3	0	0
T137	0	2	0	0
T138	0	4	0	0
T139	0	2	0	0
T140	0	4	0	0
T142	2194	0	0	0
T143	1099	0	0	0
T144	754	0	0	0
T145	546	0	0	0
T146	1321	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131608875	130	0	0
T10	21988	0	0	0
T29	8636	0	0	0
T37	477	1	0	0
T38	293	2	0	0
T39	0	2	0	0
T41	0	2	0	0
T127	4043	0	0	0
T135	0	5	0	0
T136	0	3	0	0
T137	0	2	0	0
T138	0	4	0	0
T139	0	2	0	0
T140	0	4	0	0
T142	2194	0	0	0
T143	1099	0	0	0
T144	754	0	0	0
T145	546	0	0	0
T146	1321	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	527839865	130	0	0
CgEnOn_A	527839865	125	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527839865	130	0	0
T10	87978	0	0	0
T29	63890	0	0	0
T37	2028	1	0	0
T38	1291	2	0	0
T39	0	2	0	0
T41	0	2	0	0
T127	14463	0	0	0
T135	0	5	0	0
T136	0	3	0	0
T137	0	2	0	0
T138	0	4	0	0
T139	0	2	0	0
T140	0	4	0	0
T142	8289	0	0	0
T143	4504	0	0	0
T144	3096	0	0	0
T145	2072	0	0	0
T146	5405	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527839865	125	0	0
T10	87978	0	0	0
T29	63890	0	0	0
T37	2028	1	0	0
T38	1291	2	0	0
T39	0	2	0	0
T41	0	2	0	0
T127	14463	0	0	0
T135	0	5	0	0
T136	0	3	0	0
T137	0	2	0	0
T138	0	4	0	0
T139	0	2	0	0
T140	0	4	0	0
T142	8289	0	0	0
T143	4504	0	0	0
T144	3096	0	0	0
T145	2072	0	0	0
T146	5405	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	560436205	122	0	0
CgEnOn_A	560436205	119	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	560436205	122	0	0
T10	91645	0	0	0
T29	66555	0	0	0
T38	1405	4	0	0
T39	0	1	0	0
T41	0	2	0	0
T63	0	1	0	0
T121	7229	0	0	0
T127	15067	0	0	0
T135	0	4	0	0
T136	0	3	0	0
T137	0	2	0	0
T138	0	2	0	0
T139	0	1	0	0
T140	0	5	0	0
T142	8635	0	0	0
T143	4691	0	0	0
T144	3224	0	0	0
T145	2159	0	0	0
T146	5630	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	560436205	119	0	0
T10	91645	0	0	0
T29	66555	0	0	0
T38	1405	4	0	0
T39	0	1	0	0
T41	0	2	0	0
T121	7229	0	0	0
T127	15067	0	0	0
T135	0	4	0	0
T136	0	3	0	0
T137	0	2	0	0
T138	0	2	0	0
T139	0	1	0	0
T140	0	5	0	0
T141	0	1	0	0
T142	8635	0	0	0
T143	4691	0	0	0
T144	3224	0	0	0
T145	2159	0	0	0
T146	5630	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	560436205	122	0	0
CgEnOn_A	560436205	119	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	560436205	122	0	0
T10	91645	0	0	0
T29	66555	0	0	0
T38	1405	4	0	0
T39	0	1	0	0
T41	0	2	0	0
T63	0	1	0	0
T121	7229	0	0	0
T127	15067	0	0	0
T135	0	4	0	0
T136	0	3	0	0
T137	0	2	0	0
T138	0	2	0	0
T139	0	1	0	0
T140	0	5	0	0
T142	8635	0	0	0
T143	4691	0	0	0
T144	3224	0	0	0
T145	2159	0	0	0
T146	5630	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	560436205	119	0	0
T10	91645	0	0	0
T29	66555	0	0	0
T38	1405	4	0	0
T39	0	1	0	0
T41	0	2	0	0
T121	7229	0	0	0
T127	15067	0	0	0
T135	0	4	0	0
T136	0	3	0	0
T137	0	2	0	0
T138	0	2	0	0
T139	0	1	0	0
T140	0	5	0	0
T141	0	1	0	0
T142	8635	0	0	0
T143	4691	0	0	0
T144	3224	0	0	0
T145	2159	0	0	0
T146	5630	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	268767264	117	0	0
CgEnOn_A	268767264	112	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	268767264	117	0	0
T10	43990	0	0	0
T25	0	1	0	0
T29	31947	0	0	0
T37	993	1	0	0
T38	669	4	0	0
T39	0	1	0	0
T41	0	1	0	0
T127	7232	0	0	0
T135	0	5	0	0
T136	0	2	0	0
T137	0	2	0	0
T138	0	4	0	0
T139	0	2	0	0
T142	4144	0	0	0
T143	2251	0	0	0
T144	1547	0	0	0
T145	1036	0	0	0
T146	2702	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	268767264	112	0	0
T10	43990	0	0	0
T29	31947	0	0	0
T37	993	1	0	0
T38	669	4	0	0
T39	0	1	0	0
T41	0	1	0	0
T127	7232	0	0	0
T135	0	5	0	0
T136	0	2	0	0
T137	0	2	0	0
T138	0	4	0	0
T139	0	2	0	0
T140	0	3	0	0
T142	4144	0	0	0
T143	2251	0	0	0
T144	1547	0	0	0
T145	1036	0	0	0
T146	2702	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T37,T38,T39
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	131608875	7673	0	0
CgEnOn_A	131608875	5308	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131608875	7673	0	0
T1	403682	153	0	0
T2	147690	9	0	0
T4	1221	1	0	0
T5	2999	1	0	0
T16	729	1	0	0
T17	1053	1	0	0
T18	3719	1	0	0
T19	1252	8	0	0
T20	3117	1	0	0
T21	774	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131608875	5308	0	0
T1	403682	143	0	0
T2	147690	3	0	0
T3	0	27	0	0
T4	1221	0	0	0
T5	2999	0	0	0
T9	0	19	0	0
T16	729	0	0	0
T17	1053	0	0	0
T18	3719	0	0	0
T19	1252	7	0	0
T20	3117	0	0	0
T21	774	0	0	0
T37	0	1	0	0
T38	0	2	0	0
T68	0	1	0	0
T70	0	8	0	0
T147	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T37,T38,T39
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	263218881	7727	0	0
CgEnOn_A	263218881	5362	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	263218881	7727	0	0
T1	807368	148	0	0
T2	295379	10	0	0
T4	2444	1	0	0
T5	5999	1	0	0
T16	1457	1	0	0
T17	2107	1	0	0
T18	7437	1	0	0
T19	2504	11	0	0
T20	6235	1	0	0
T21	1549	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	263218881	5362	0	0
T1	807368	138	0	0
T2	295379	4	0	0
T3	0	29	0	0
T4	2444	0	0	0
T5	5999	0	0	0
T9	0	19	0	0
T16	1457	0	0	0
T17	2107	0	0	0
T18	7437	0	0	0
T19	2504	10	0	0
T20	6235	0	0	0
T21	1549	0	0	0
T37	0	1	0	0
T38	0	2	0	0
T68	0	1	0	0
T70	0	6	0	0
T147	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T37,T38,T39
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	527839865	7753	0	0
CgEnOn_A	527839865	5383	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527839865	7753	0	0
T1	161508	152	0	0
T2	591259	10	0	0
T4	4318	1	0	0
T5	9981	1	0	0
T16	2939	1	0	0
T17	3840	1	0	0
T18	14927	1	0	0
T19	5075	8	0	0
T20	12577	1	0	0
T21	3136	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527839865	5383	0	0
T1	161508	142	0	0
T2	591259	4	0	0
T3	0	26	0	0
T4	4318	0	0	0
T5	9981	0	0	0
T9	0	19	0	0
T16	2939	0	0	0
T17	3840	0	0	0
T18	14927	0	0	0
T19	5075	7	0	0
T20	12577	0	0	0
T21	3136	0	0	0
T37	0	1	0	0
T38	0	2	0	0
T68	0	1	0	0
T70	0	6	0	0
T147	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T37,T38,T39
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	268767264	7707	0	0
CgEnOn_A	268767264	5336	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	268767264	7707	0	0
T1	817662	145	0	0
T2	318685	10	0	0
T4	2160	1	0	0
T5	4991	1	0	0
T16	1469	1	0	0
T17	1920	1	0	0
T18	7464	1	0	0
T19	2537	9	0	0
T20	6288	1	0	0
T21	1568	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	268767264	5336	0	0
T1	817662	135	0	0
T2	318685	4	0	0
T3	0	28	0	0
T4	2160	0	0	0
T5	4991	0	0	0
T9	0	22	0	0
T16	1469	0	0	0
T17	1920	0	0	0
T18	7464	0	0	0
T19	2537	8	0	0
T20	6288	0	0	0
T21	1568	0	0	0
T37	0	1	0	0
T38	0	4	0	0
T68	0	1	0	0
T70	0	6	0	0
T147	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T16,T18
1	1	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	560436205	3929	0	0
CgEnOn_A	560436205	3926	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	560436205	3929	0	0
T1	170943	71	0	0
T2	669915	4	0	0
T3	0	14	0	0
T4	4499	0	0	0
T5	10398	0	0	0
T9	0	17	0	0
T16	3062	3	0	0
T17	4000	0	0	0
T18	15549	7	0	0
T19	5286	0	0	0
T20	13101	10	0	0
T21	3266	11	0	0
T68	0	1	0	0
T69	0	9	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	560436205	3926	0	0
T1	170943	71	0	0
T2	669915	4	0	0
T3	0	14	0	0
T4	4499	0	0	0
T5	10398	0	0	0
T9	0	17	0	0
T16	3062	3	0	0
T17	4000	0	0	0
T18	15549	7	0	0
T19	5286	0	0	0
T20	13101	10	0	0
T21	3266	11	0	0
T68	0	1	0	0
T69	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T16,T18
1	1	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	560436205	3838	0	0
CgEnOn_A	560436205	3835	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	560436205	3838	0	0
T1	170943	58	0	0
T2	669915	4	0	0
T3	0	17	0	0
T4	4499	0	0	0
T5	10398	0	0	0
T9	0	17	0	0
T16	3062	6	0	0
T17	4000	0	0	0
T18	15549	4	0	0
T19	5286	0	0	0
T20	13101	12	0	0
T21	3266	11	0	0
T68	0	1	0	0
T69	0	11	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	560436205	3835	0	0
T1	170943	58	0	0
T2	669915	4	0	0
T3	0	17	0	0
T4	4499	0	0	0
T5	10398	0	0	0
T9	0	17	0	0
T16	3062	6	0	0
T17	4000	0	0	0
T18	15549	4	0	0
T19	5286	0	0	0
T20	13101	12	0	0
T21	3266	11	0	0
T68	0	1	0	0
T69	0	11	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T16,T18
1	1	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	560436205	3906	0	0
CgEnOn_A	560436205	3903	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	560436205	3906	0	0
T1	170943	69	0	0
T2	669915	4	0	0
T3	0	19	0	0
T4	4499	0	0	0
T5	10398	0	0	0
T9	0	18	0	0
T16	3062	5	0	0
T17	4000	0	0	0
T18	15549	7	0	0
T19	5286	0	0	0
T20	13101	10	0	0
T21	3266	9	0	0
T68	0	1	0	0
T69	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	560436205	3903	0	0
T1	170943	69	0	0
T2	669915	4	0	0
T3	0	19	0	0
T4	4499	0	0	0
T5	10398	0	0	0
T9	0	18	0	0
T16	3062	5	0	0
T17	4000	0	0	0
T18	15549	7	0	0
T19	5286	0	0	0
T20	13101	10	0	0
T21	3266	9	0	0
T68	0	1	0	0
T69	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T16,T18
1	1	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	560436205	3894	0	0
CgEnOn_A	560436205	3891	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	560436205	3894	0	0
T1	170943	73	0	0
T2	669915	4	0	0
T3	0	16	0	0
T4	4499	0	0	0
T5	10398	0	0	0
T9	0	15	0	0
T16	3062	5	0	0
T17	4000	0	0	0
T18	15549	8	0	0
T19	5286	0	0	0
T20	13101	9	0	0
T21	3266	8	0	0
T68	0	1	0	0
T69	0	7	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	560436205	3891	0	0
T1	170943	73	0	0
T2	669915	4	0	0
T3	0	16	0	0
T4	4499	0	0	0
T5	10398	0	0	0
T9	0	15	0	0
T16	3062	5	0	0
T17	4000	0	0	0
T18	15549	8	0	0
T19	5286	0	0	0
T20	13101	9	0	0
T21	3266	8	0	0
T68	0	1	0	0
T69	0	7	0	0