Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	561897	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3112721

1

T4

47

T1

108

T5

21

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	906362	1			T4	68		T1	22		T5	28
values[0x0]	1274925	1			T4	27		T1	94		T5	10
values[0x1]	1493331	1			T4	24		T1	118		T5	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	314125	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3360493

1

T4

62

T1

157

T5

28

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15209	1			T1	1		T2	195		T3	664
valid_sources[0x01]	14019	1			T1	2		T2	181		T3	657
valid_sources[0x02]	16078	1			T1	3		T2	179		T3	783
valid_sources[0x03]	15657	1			T16	1		T2	164		T3	598
valid_sources[0x04]	14802	1			T1	3		T2	214		T3	577
valid_sources[0x05]	14302	1			T5	1		T16	1		T2	184
valid_sources[0x06]	15200	1			T1	1		T5	1		T2	178
valid_sources[0x07]	14590	1			T2	141		T3	767		T22	2
valid_sources[0x08]	14865	1			T16	2		T2	221		T3	637
valid_sources[0x09]	14009	1			T1	1		T2	137		T3	681
valid_sources[0x0a]	13183	1			T1	1		T16	8		T2	180
valid_sources[0x0b]	15200	1			T5	1		T2	168		T3	760
valid_sources[0x0c]	13965	1			T1	1		T2	156		T17	18
valid_sources[0x0d]	13265	1			T16	2		T2	205		T3	720
valid_sources[0x0e]	15560	1			T1	1		T2	166		T18	5
valid_sources[0x0f]	13327	1			T5	3		T2	176		T3	494
valid_sources[0x10]	14084	1			T2	177		T3	656		T29	2
valid_sources[0x11]	15298	1			T2	195		T3	636		T28	4
valid_sources[0x12]	13412	1			T16	1		T2	163		T3	548
valid_sources[0x13]	14581	1			T2	164		T3	554		T28	4
valid_sources[0x14]	17005	1			T1	2		T16	1		T2	116
valid_sources[0x15]	16297	1			T1	1		T2	238		T3	598
valid_sources[0x16]	14432	1			T1	1		T16	1		T2	201
valid_sources[0x17]	13876	1			T1	2		T2	172		T3	608
valid_sources[0x18]	13806	1			T1	1		T2	158		T3	493
valid_sources[0x19]	14768	1			T2	201		T3	722		T22	1
valid_sources[0x1a]	14868	1			T1	1		T2	199		T3	621
valid_sources[0x1b]	13466	1			T1	1		T2	163		T3	596
valid_sources[0x1c]	14158	1			T1	1		T2	135		T3	604
valid_sources[0x1d]	16065	1			T1	1		T2	145		T3	668
valid_sources[0x1e]	13508	1			T2	177		T3	432		T22	2
valid_sources[0x1f]	13668	1			T2	114		T3	630		T28	3
valid_sources[0x20]	14152	1			T2	196		T3	741		T21	2
valid_sources[0x21]	16210	1			T1	4		T5	1		T2	152
valid_sources[0x22]	14435	1			T2	176		T3	639		T22	3
valid_sources[0x23]	15222	1			T5	2		T2	184		T3	627
valid_sources[0x24]	13796	1			T2	137		T3	581		T21	1
valid_sources[0x25]	14121	1			T1	1		T2	165		T3	624
valid_sources[0x26]	15241	1			T1	1		T2	149		T3	584
valid_sources[0x27]	13871	1			T2	191		T3	628		T28	2
valid_sources[0x28]	14676	1			T5	3		T2	222		T3	592
valid_sources[0x29]	14203	1			T1	1		T2	156		T3	940
valid_sources[0x2a]	13306	1			T1	1		T16	1		T2	177
valid_sources[0x2b]	13879	1			T2	145		T3	681		T22	5
valid_sources[0x2c]	15298	1			T1	3		T2	175		T3	617
valid_sources[0x2d]	14314	1			T2	172		T3	644		T22	4
valid_sources[0x2e]	15883	1			T1	1		T2	147		T3	506
valid_sources[0x2f]	14872	1			T1	1		T2	171		T3	470
valid_sources[0x30]	14366	1			T16	2		T2	146		T3	676
valid_sources[0x31]	13849	1			T1	1		T2	160		T3	615
valid_sources[0x32]	15223	1			T1	1		T2	134		T3	793
valid_sources[0x33]	14057	1			T1	2		T5	2		T2	200
valid_sources[0x34]	15443	1			T16	1		T2	184		T3	747
valid_sources[0x35]	12666	1			T1	1		T5	1		T2	153
valid_sources[0x36]	14207	1			T2	162		T3	683		T22	2
valid_sources[0x37]	13523	1			T16	1		T2	159		T3	477
valid_sources[0x38]	13415	1			T1	4		T5	2		T16	1
valid_sources[0x39]	13742	1			T2	110		T3	458		T21	1
valid_sources[0x3a]	14114	1			T1	1		T16	1		T2	158
valid_sources[0x3b]	13704	1			T1	1		T2	133		T3	649
valid_sources[0x3c]	13286	1			T1	2		T2	123		T3	560
valid_sources[0x3d]	13328	1			T1	3		T2	162		T3	554
valid_sources[0x3e]	15165	1			T1	2		T2	205		T3	559
valid_sources[0x3f]	13662	1			T1	1		T5	1		T16	1
valid_sources[0x40]	16154	1			T1	3		T16	1		T2	158
valid_sources[0x41]	14951	1			T1	3		T16	1		T2	133
valid_sources[0x42]	15241	1			T2	165		T3	622		T29	4
valid_sources[0x43]	13620	1			T2	147		T3	761		T21	1
valid_sources[0x44]	14462	1			T2	149		T3	657		T21	1
valid_sources[0x45]	14581	1			T1	3		T2	149		T3	535
valid_sources[0x46]	14830	1			T1	1		T2	130		T3	676
valid_sources[0x47]	13562	1			T1	2		T2	193		T3	718
valid_sources[0x48]	14911	1			T2	144		T17	15		T3	584
valid_sources[0x49]	13657	1			T1	1		T16	1		T2	161
valid_sources[0x4a]	14327	1			T1	1		T2	160		T3	595
valid_sources[0x4b]	13115	1			T2	208		T3	719		T28	1
valid_sources[0x4c]	14320	1			T2	147		T3	831		T21	2
valid_sources[0x4d]	13305	1			T2	99		T3	782		T28	4
valid_sources[0x4e]	16322	1			T1	1		T2	212		T3	650
valid_sources[0x4f]	13601	1			T2	118		T3	662		T22	1
valid_sources[0x50]	15107	1			T4	119		T5	1		T2	131
valid_sources[0x51]	14443	1			T1	1		T2	137		T3	719
valid_sources[0x52]	15663	1			T1	1		T2	135		T3	684
valid_sources[0x53]	14672	1			T2	203		T3	908		T28	2
valid_sources[0x54]	13803	1			T2	135		T3	723		T29	4
valid_sources[0x55]	14927	1			T1	1		T2	179		T3	785
valid_sources[0x56]	14003	1			T1	2		T16	5		T2	171
valid_sources[0x57]	13191	1			T1	1		T2	190		T3	723
valid_sources[0x58]	15396	1			T2	164		T3	780		T28	7
valid_sources[0x59]	14381	1			T1	3		T2	207		T3	534
valid_sources[0x5a]	14231	1			T1	2		T2	173		T3	762
valid_sources[0x5b]	14768	1			T1	1		T2	207		T3	546
valid_sources[0x5c]	15198	1			T1	1		T2	139		T3	487
valid_sources[0x5d]	13519	1			T16	2		T2	176		T3	716
valid_sources[0x5e]	13308	1			T2	248		T3	701		T21	1
valid_sources[0x5f]	12830	1			T1	3		T16	2		T2	167
valid_sources[0x60]	15614	1			T2	216		T3	747		T22	2
valid_sources[0x61]	14617	1			T1	1		T2	172		T3	576
valid_sources[0x62]	13632	1			T16	1		T2	208		T3	778
valid_sources[0x63]	15199	1			T1	5		T2	174		T3	665
valid_sources[0x64]	13503	1			T1	2		T16	10		T2	180
valid_sources[0x65]	12973	1			T2	174		T3	686		T29	4
valid_sources[0x66]	14639	1			T1	1		T5	1		T16	3
valid_sources[0x67]	15810	1			T1	2		T16	2		T2	143
valid_sources[0x68]	12978	1			T2	179		T3	667		T28	4
valid_sources[0x69]	16341	1			T1	1		T16	6		T2	114
valid_sources[0x6a]	14831	1			T1	3		T5	1		T2	138
valid_sources[0x6b]	13610	1			T16	1		T2	117		T3	799
valid_sources[0x6c]	13850	1			T5	1		T16	5		T2	196
valid_sources[0x6d]	14944	1			T1	3		T2	183		T3	658
valid_sources[0x6e]	14822	1			T2	194		T3	592		T22	1
valid_sources[0x6f]	14370	1			T2	152		T3	729		T22	1
valid_sources[0x70]	15334	1			T16	1		T2	179		T3	666
valid_sources[0x71]	13387	1			T1	1		T2	207		T3	553
valid_sources[0x72]	14207	1			T1	1		T2	146		T3	733
valid_sources[0x73]	13472	1			T2	120		T3	547		T28	1
valid_sources[0x74]	13938	1			T1	1		T16	1		T2	172
valid_sources[0x75]	14967	1			T16	1		T2	190		T3	585
valid_sources[0x76]	14021	1			T1	1		T2	168		T3	745
valid_sources[0x77]	13485	1			T1	1		T5	1		T2	199
valid_sources[0x78]	14510	1			T1	2		T2	99		T3	754
valid_sources[0x79]	12783	1			T5	1		T2	163		T3	614
valid_sources[0x7a]	14490	1			T2	259		T3	650		T28	2
valid_sources[0x7b]	15613	1			T1	1		T2	191		T3	768
valid_sources[0x7c]	14223	1			T1	1		T2	193		T3	704
valid_sources[0x7d]	13286	1			T16	1		T2	179		T3	667
valid_sources[0x7e]	14378	1			T1	1		T5	1		T2	145
valid_sources[0x7f]	14814	1			T1	1		T2	195		T3	571
valid_sources[0x80]	14684	1			T1	1		T2	152		T3	562

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

786453

1

T4

32

T1

13

T5

17

values[0x0]

all_enables

biggest_size

1186988

1

T4

12

T1

63

T5

3

values[0x1]

all_enables

biggest_size

1139280

1

T4

3

T1

32

T5

1