Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T17,T3
0	1	Covered	T2,T17,T3
1	0	Covered	T4,T1,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T17,T3
1	0	Covered	T27,T36,T38
1	1	Covered	T4,T1,T5

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	904004987	11941	0	0
GateOpen_A	904004987	18929	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	904004987	11941	0	0
T2	1488528	81	0	0
T3	1174825	166	0	0
T9	0	76	0	0
T10	0	188	0	0
T12	0	44	0	0
T17	4149	33	0	0
T18	2378	0	0	0
T19	6335	0	0	0
T20	193736	0	0	0
T21	5006	0	0	0
T22	194138	0	0	0
T26	13079	0	0	0
T27	8368	12	0	0
T36	0	15	0	0
T113	0	4	0	0
T159	0	9	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	904004987	18929	0	0
T1	249234	4	0	0
T2	1488528	93	0	0
T3	1174825	182	0	0
T5	4855	0	0	0
T16	15407	0	0	0
T17	4149	33	0	0
T18	2378	4	0	0
T19	6335	4	0	0
T20	193736	0	0	0
T21	5006	0	0	0
T26	0	4	0	0
T27	0	16	0	0
T28	0	48	0	0
T31	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T17,T3
0	1	Covered	T2,T17,T3
1	0	Covered	T4,T1,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T17,T3
1	0	Covered	T27,T36,T37
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	99633395	2863	0	0
GateOpen_A	99633395	4608	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99633395	2863	0	0
T2	822520	18	0	0
T3	651966	40	0	0
T9	0	15	0	0
T10	0	45	0	0
T12	0	10	0	0
T17	450	7	0	0
T18	264	0	0	0
T19	689	0	0	0
T20	20560	0	0	0
T21	559	0	0	0
T22	20600	0	0	0
T26	1447	0	0	0
T27	909	3	0	0
T36	0	4	0	0
T113	0	1	0	0
T159	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99633395	4608	0	0
T1	27682	1	0	0
T2	822520	21	0	0
T3	651966	44	0	0
T5	536	0	0	0
T16	1706	0	0	0
T17	450	7	0	0
T18	264	1	0	0
T19	689	1	0	0
T20	20560	0	0	0
T21	559	0	0	0
T26	0	1	0	0
T27	0	4	0	0
T28	0	12	0	0
T31	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T17,T3
0	1	Covered	T2,T17,T3
1	0	Covered	T4,T1,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T17,T3
1	0	Covered	T27,T36,T37
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	199267500	3028	0	0
GateOpen_A	199267500	4773	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199267500	3028	0	0
T2	164504	21	0	0
T3	130393	45	0	0
T9	0	22	0	0
T10	0	50	0	0
T12	0	11	0	0
T17	900	7	0	0
T18	528	0	0	0
T19	1377	0	0	0
T20	41119	0	0	0
T21	1118	0	0	0
T22	41200	0	0	0
T26	2894	0	0	0
T27	1818	3	0	0
T36	0	4	0	0
T113	0	1	0	0
T159	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199267500	4773	0	0
T1	55363	1	0	0
T2	164504	24	0	0
T3	130393	49	0	0
T5	1071	0	0	0
T16	3411	0	0	0
T17	900	7	0	0
T18	528	1	0	0
T19	1377	1	0	0
T20	41119	0	0	0
T21	1118	0	0	0
T26	0	1	0	0
T27	0	4	0	0
T28	0	12	0	0
T31	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T17,T3
0	1	Covered	T2,T17,T3
1	0	Covered	T4,T1,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T17,T3
1	0	Covered	T27,T36,T37
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	400261923	3021	0	0
GateOpen_A	400261923	4769	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400261923	3021	0	0
T2	329915	20	0	0
T3	260831	41	0	0
T9	0	19	0	0
T10	0	45	0	0
T12	0	11	0	0
T17	1866	10	0	0
T18	1058	0	0	0
T19	2846	0	0	0
T20	82276	0	0	0
T21	2219	0	0	0
T22	82464	0	0	0
T26	5825	0	0	0
T27	3700	3	0	0
T36	0	4	0	0
T113	0	1	0	0
T159	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400261923	4769	0	0
T1	110791	1	0	0
T2	329915	23	0	0
T3	260831	45	0	0
T5	2165	0	0	0
T16	6860	0	0	0
T17	1866	10	0	0
T18	1058	1	0	0
T19	2846	1	0	0
T20	82276	0	0	0
T21	2219	0	0	0
T26	0	1	0	0
T27	0	4	0	0
T28	0	12	0	0
T31	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T17,T3
0	1	Covered	T2,T17,T3
1	0	Covered	T4,T1,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T17,T3
1	0	Covered	T27,T36,T38
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	204842169	3029	0	0
GateOpen_A	204842169	4779	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	204842169	3029	0	0
T2	171589	22	0	0
T3	131635	40	0	0
T9	0	20	0	0
T10	0	48	0	0
T12	0	12	0	0
T17	933	9	0	0
T18	528	0	0	0
T19	1423	0	0	0
T20	49781	0	0	0
T21	1110	0	0	0
T22	49874	0	0	0
T26	2913	0	0	0
T27	1941	3	0	0
T36	0	3	0	0
T113	0	1	0	0
T159	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	204842169	4779	0	0
T1	55398	1	0	0
T2	171589	25	0	0
T3	131635	44	0	0
T5	1083	0	0	0
T16	3430	0	0	0
T17	933	9	0	0
T18	528	1	0	0
T19	1423	1	0	0
T20	49781	0	0	0
T21	1110	0	0	0
T26	0	1	0	0
T27	0	4	0	0
T28	0	12	0	0
T31	0	1	0	0