Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	673452575	79830	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673452575	79830	0	0
T1	571285	110	0	0
T2	865145	254	0	0
T3	2339655	539	0	0
T5	10715	0	0	0
T9	0	798	0	0
T10	0	1294	0	0
T11	0	508	0	0
T12	0	464	0	0
T13	0	480	0	0
T14	0	493	0	0
T15	0	314	0	0
T16	11790	0	0	0
T17	9230	0	0	0
T18	5285	0	0	0
T19	7555	0	0	0
T20	371215	0	0	0
T21	11555	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	134690515	11774	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134690515	11774	0	0
T1	114257	15	0	0
T2	173029	36	0	0
T3	467931	91	0	0
T5	2143	0	0	0
T9	0	105	0	0
T10	0	188	0	0
T11	0	65	0	0
T12	0	68	0	0
T13	0	75	0	0
T14	0	73	0	0
T15	0	45	0	0
T16	2358	0	0	0
T17	1846	0	0	0
T18	1057	0	0	0
T19	1511	0	0	0
T20	74243	0	0	0
T21	2311	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	134690515	11724	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134690515	11724	0	0
T1	114257	14	0	0
T2	173029	36	0	0
T3	467931	91	0	0
T5	2143	0	0	0
T9	0	105	0	0
T10	0	186	0	0
T11	0	74	0	0
T12	0	67	0	0
T13	0	74	0	0
T14	0	63	0	0
T15	0	45	0	0
T16	2358	0	0	0
T17	1846	0	0	0
T18	1057	0	0	0
T19	1511	0	0	0
T20	74243	0	0	0
T21	2311	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	134690515	16074	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134690515	16074	0	0
T1	114257	23	0	0
T2	173029	57	0	0
T3	467931	109	0	0
T5	2143	0	0	0
T9	0	163	0	0
T10	0	262	0	0
T11	0	101	0	0
T12	0	93	0	0
T13	0	98	0	0
T14	0	95	0	0
T15	0	70	0	0
T16	2358	0	0	0
T17	1846	0	0	0
T18	1057	0	0	0
T19	1511	0	0	0
T20	74243	0	0	0
T21	2311	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	134690515	15994	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134690515	15994	0	0
T1	114257	22	0	0
T2	173029	49	0	0
T3	467931	110	0	0
T5	2143	0	0	0
T9	0	160	0	0
T10	0	259	0	0
T11	0	99	0	0
T12	0	94	0	0
T13	0	99	0	0
T14	0	100	0	0
T15	0	60	0	0
T16	2358	0	0	0
T17	1846	0	0	0
T18	1057	0	0	0
T19	1511	0	0	0
T20	74243	0	0	0
T21	2311	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	134690515	24264	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134690515	24264	0	0
T1	114257	36	0	0
T2	173029	76	0	0
T3	467931	138	0	0
T5	2143	0	0	0
T9	0	265	0	0
T10	0	399	0	0
T11	0	169	0	0
T12	0	142	0	0
T13	0	134	0	0
T14	0	162	0	0
T15	0	94	0	0
T16	2358	0	0	0
T17	1846	0	0	0
T18	1057	0	0	0
T19	1511	0	0	0
T20	74243	0	0	0
T21	2311	0	0	0