Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T2,T3,T28

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	134690515	132064574	0	0
AllClkBypReqTrue_A	134690515	113519	0	0
IoClkBypReqFalse_A	134690515	131992919	0	2415
IoClkBypReqTrue_A	134690515	180336	0	0
LcClkBypAckFalse_A	134690515	132070130	0	0
LcClkBypAckTrue_A	134690515	107963	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134690515	132064574	0	0
T1	114257	114145	0	0
T2	173029	171693	0	0
T3	467931	467382	0	0
T4	2591	2579	0	0
T5	2143	2036	0	0
T16	2358	2330	0	0
T17	1846	1658	0	0
T18	1057	938	0	0
T19	1511	1417	0	0
T20	74243	74148	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134690515	113519	0	0
T2	173029	758	0	0
T3	467931	724	0	0
T9	0	345	0	0
T10	0	1280	0	0
T12	0	360	0	0
T13	0	279	0	0
T17	1846	0	0	0
T18	1057	24	0	0
T19	1511	0	0	0
T20	74243	0	0	0
T21	2311	0	0	0
T22	106608	0	0	0
T26	1455	0	0	0
T27	1043	0	0	0
T110	0	52	0	0
T111	0	225	0	0
T112	0	195	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134690515	131992919	0	2415
T1	114257	114143	0	3
T2	173029	171624	0	3
T3	467931	467272	0	3
T4	2591	2577	0	3
T5	2143	2034	0	3
T16	2358	2328	0	3
T17	1846	1656	0	3
T18	1057	936	0	3
T19	1511	1415	0	3
T20	74243	74146	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134690515	180336	0	0
T2	173029	1437	0	0
T3	467931	1804	0	0
T9	0	503	0	0
T10	0	1653	0	0
T12	0	631	0	0
T17	1846	0	0	0
T18	1057	24	0	0
T19	1511	0	0	0
T20	74243	0	0	0
T21	2311	236	0	0
T22	106608	0	0	0
T26	1455	0	0	0
T27	1043	0	0	0
T110	0	39	0	0
T111	0	313	0	0
T112	0	330	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134690515	132070130	0	0
T1	114257	114145	0	0
T2	173029	171661	0	0
T3	467931	467341	0	0
T4	2591	2579	0	0
T5	2143	2036	0	0
T16	2358	2330	0	0
T17	1846	1658	0	0
T18	1057	947	0	0
T19	1511	1417	0	0
T20	74243	74148	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134690515	107963	0	0
T2	173029	1077	0	0
T3	467931	1138	0	0
T9	0	327	0	0
T10	0	1099	0	0
T12	0	462	0	0
T17	1846	0	0	0
T18	1057	15	0	0
T19	1511	0	0	0
T20	74243	0	0	0
T21	2311	112	0	0
T22	106608	0	0	0
T26	1455	0	0	0
T27	1043	0	0	0
T110	0	33	0	0
T111	0	217	0	0
T112	0	209	0	0