Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1705908636	14100	0	0
TransStop_A	1705908636	7173	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1705908636	14100	0	0
T1	461644	0	0	0
T2	1417888	134	0	0
T3	1095024	203	0	0
T4	86364	32	0	0
T5	9024	13	0	0
T9	0	67	0	0
T10	0	168	0	0
T12	0	12	0	0
T16	28584	44	0	0
T17	7776	0	0	0
T18	4404	0	0	0
T19	11860	0	0	0
T20	462824	0	0	0
T26	0	18	0	0
T113	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1705908636	7173	0	0
T1	461644	0	0	0
T2	1417888	70	0	0
T3	1095024	103	0	0
T4	86364	12	0	0
T5	9024	5	0	0
T9	0	26	0	0
T10	0	90	0	0
T12	0	8	0	0
T13	0	5	0	0
T16	28584	22	0	0
T17	7776	0	0	0
T18	4404	0	0	0
T19	11860	0	0	0
T20	462824	0	0	0
T26	0	13	0	0
T113	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	426477159	3523	0	0
TransStop_A	426477159	1787	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426477159	3523	0	0
T1	115411	0	0	0
T2	354472	33	0	0
T3	273756	49	0	0
T4	21591	10	0	0
T5	2256	2	0	0
T9	0	15	0	0
T10	0	46	0	0
T12	0	3	0	0
T16	7146	12	0	0
T17	1944	0	0	0
T18	1101	0	0	0
T19	2965	0	0	0
T20	115706	0	0	0
T26	0	6	0	0
T113	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426477159	1787	0	0
T1	115411	0	0	0
T2	354472	17	0	0
T3	273756	24	0	0
T4	21591	4	0	0
T5	2256	1	0	0
T9	0	4	0	0
T10	0	23	0	0
T12	0	2	0	0
T16	7146	6	0	0
T17	1944	0	0	0
T18	1101	0	0	0
T19	2965	0	0	0
T20	115706	0	0	0
T26	0	5	0	0
T113	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	426477159	3532	0	0
TransStop_A	426477159	1790	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426477159	3532	0	0
T1	115411	0	0	0
T2	354472	34	0	0
T3	273756	50	0	0
T4	21591	6	0	0
T5	2256	3	0	0
T9	0	14	0	0
T10	0	41	0	0
T12	0	3	0	0
T16	7146	11	0	0
T17	1944	0	0	0
T18	1101	0	0	0
T19	2965	0	0	0
T20	115706	0	0	0
T26	0	2	0	0
T113	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426477159	1790	0	0
T1	115411	0	0	0
T2	354472	18	0	0
T3	273756	27	0	0
T4	21591	2	0	0
T5	2256	1	0	0
T9	0	5	0	0
T10	0	24	0	0
T12	0	2	0	0
T13	0	5	0	0
T16	7146	6	0	0
T17	1944	0	0	0
T18	1101	0	0	0
T19	2965	0	0	0
T20	115706	0	0	0
T113	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	426477159	3479	0	0
TransStop_A	426477159	1784	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426477159	3479	0	0
T1	115411	0	0	0
T2	354472	30	0	0
T3	273756	53	0	0
T4	21591	9	0	0
T5	2256	4	0	0
T9	0	16	0	0
T10	0	43	0	0
T12	0	3	0	0
T16	7146	11	0	0
T17	1944	0	0	0
T18	1101	0	0	0
T19	2965	0	0	0
T20	115706	0	0	0
T26	0	5	0	0
T113	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426477159	1784	0	0
T1	115411	0	0	0
T2	354472	16	0	0
T3	273756	27	0	0
T4	21591	4	0	0
T5	2256	1	0	0
T9	0	8	0	0
T10	0	22	0	0
T12	0	2	0	0
T16	7146	5	0	0
T17	1944	0	0	0
T18	1101	0	0	0
T19	2965	0	0	0
T20	115706	0	0	0
T26	0	4	0	0
T113	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	426477159	3566	0	0
TransStop_A	426477159	1812	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426477159	3566	0	0
T1	115411	0	0	0
T2	354472	37	0	0
T3	273756	51	0	0
T4	21591	7	0	0
T5	2256	4	0	0
T9	0	22	0	0
T10	0	38	0	0
T12	0	3	0	0
T16	7146	10	0	0
T17	1944	0	0	0
T18	1101	0	0	0
T19	2965	0	0	0
T20	115706	0	0	0
T26	0	5	0	0
T113	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426477159	1812	0	0
T1	115411	0	0	0
T2	354472	19	0	0
T3	273756	25	0	0
T4	21591	2	0	0
T5	2256	2	0	0
T9	0	9	0	0
T10	0	21	0	0
T12	0	2	0	0
T16	7146	5	0	0
T17	1944	0	0	0
T18	1101	0	0	0
T19	2965	0	0	0
T20	115706	0	0	0
T26	0	4	0	0
T113	0	1	0	0