Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	135605050	4522933	0	0
clk_enables_rd_A	135605050	33893	0	0
clk_hints_rd_A	135605050	29839	0	0
extclk_ctrl_rd_A	135605050	37496	0	0
extclk_ctrl_regwen_rd_A	135605050	28726	0	0
jitter_enable_rd_A	135605050	42328	0	0
jitter_regwen_rd_A	135605050	32777	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135605050	4522933	0	0
T2	173029	56456	0	0
T3	467931	228349	0	0
T9	0	33124	0	0
T10	0	127317	0	0
T15	0	41460	0	0
T17	1846	0	0	0
T18	1057	0	0	0
T19	1511	0	0	0
T20	74243	0	0	0
T21	2311	0	0	0
T22	106608	0	0	0
T26	1455	0	0	0
T27	1043	0	0	0
T33	0	77243	0	0
T66	0	119107	0	0
T67	0	58374	0	0
T68	0	108344	0	0
T69	0	127208	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135605050	33893	0	0
T2	173029	1191	0	0
T3	467931	0	0	0
T15	0	1400	0	0
T17	1846	0	0	0
T18	1057	0	0	0
T19	1511	0	0	0
T20	74243	0	0	0
T21	2311	0	0	0
T22	106608	0	0	0
T26	1455	0	0	0
T27	1043	0	0	0
T66	0	4567	0	0
T67	0	2166	0	0
T85	0	1	0	0
T114	0	7	0	0
T136	0	1	0	0
T137	0	486	0	0
T138	0	2	0	0
T139	0	2	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135605050	29839	0	0
T2	173029	885	0	0
T3	467931	0	0	0
T15	0	1420	0	0
T17	1846	0	0	0
T18	1057	0	0	0
T19	1511	0	0	0
T20	74243	0	0	0
T21	2311	0	0	0
T22	106608	0	0	0
T26	1455	0	0	0
T27	1043	0	0	0
T50	0	7	0	0
T66	0	3748	0	0
T67	0	1921	0	0
T114	0	6	0	0
T136	0	7	0	0
T137	0	539	0	0
T138	0	6	0	0
T139	0	8	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135605050	37496	0	0
T2	173029	1218	0	0
T3	467931	0	0	0
T15	0	1573	0	0
T17	1846	0	0	0
T18	1057	0	0	0
T19	1511	0	0	0
T20	74243	0	0	0
T21	2311	0	0	0
T22	106608	0	0	0
T26	1455	0	0	0
T27	1043	0	0	0
T110	0	14	0	0
T111	0	34	0	0
T112	0	40	0	0
T140	0	40	0	0
T141	0	35	0	0
T142	0	49	0	0
T143	0	11	0	0
T144	0	66	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135605050	28726	0	0
T2	173029	950	0	0
T3	467931	0	0	0
T15	0	1396	0	0
T17	1846	0	0	0
T18	1057	0	0	0
T19	1511	0	0	0
T20	74243	0	0	0
T21	2311	0	0	0
T22	106608	0	0	0
T26	1455	0	0	0
T27	1043	0	0	0
T66	0	4195	0	0
T67	0	1985	0	0
T137	0	376	0	0
T143	0	3	0	0
T145	0	16	0	0
T146	0	3	0	0
T147	0	38	0	0
T148	0	75	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135605050	42328	0	0
T2	173029	1538	0	0
T3	467931	0	0	0
T15	0	2226	0	0
T17	1846	0	0	0
T18	1057	0	0	0
T19	1511	0	0	0
T20	74243	0	0	0
T21	2311	0	0	0
T22	106608	0	0	0
T26	1455	0	0	0
T27	1043	0	0	0
T66	0	6297	0	0
T67	0	3137	0	0
T85	0	106	0	0
T114	0	246	0	0
T136	0	113	0	0
T137	0	426	0	0
T138	0	226	0	0
T139	0	110	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135605050	32777	0	0
T2	173029	1486	0	0
T3	467931	0	0	0
T15	0	1600	0	0
T17	1846	0	0	0
T18	1057	0	0	0
T19	1511	0	0	0
T20	74243	0	0	0
T21	2311	0	0	0
T22	106608	0	0	0
T26	1455	0	0	0
T27	1043	0	0	0
T66	0	4553	0	0
T67	0	2116	0	0
T137	0	549	0	0
T149	0	1417	0	0
T150	0	4122	0	0
T151	0	3324	0	0
T152	0	4626	0	0
T153	0	752	0	0